The Industry has been using Computational Fluid Dynamics (CFD) and Finite Element Analysis (FEA) for thermal and mechanical modeling of IC packages for many years. What was already practiced as an engineering-art within packaging organizations for monolithic IC packages has now become more complex due to the need for collaboration across organizational walls in the case of 3D stacking. The holistic solution needed for collaborative engineering of 3D stacking process calls for newer methodologies and information exchange protocols.
One particular necessity while building low power System on Chip (SOC) is the methodology needed to ensure package specific thermal feasibility of IC stacking options at physical layout stage of the 3D IC design. A methodology built on the technique to be presented will avert the unintended consequences of stacked IC hot spot alignment during system operation. The presentation will include a validation of the technique by comparison with traditional thermal modeling technique.
The ability to fabricate such stacks using an evolving supply chain of foundry-OSAT combination is equally crucial to the viability and reliability of the packaged SOC. A process focused modeling tool for understanding the warpage, stress, and Chip Package Interaction (CPI) implications of assembly strategy choices is valuable for ensuring time to market at minimal technology development costs. The presentation will include a modeling case study with quantitative data of warpage and stress implications of process, material and stacking choices.
This presentation will introduce the tools and techniques for collaborative chip stack thermal and assembly process modeling with in-depth discussions on inputs needed, gaps in existing modeling methodologies and output metrics of engineering relevance.
