As package design complexity increases, and design cycle times are increasingly subject to aggressively truncated timelines, the need to achieve efficient one-pass physical routing of complex, I/O dense, IC packages becomes critical. Critical high-speed interfaces such as DDR2, DDR3, PCI Express, and HDMI now constitute a high percentage of signals in an electronic package. This presentation will focus on utilizing an integrated route-planning tool to quickly and effectively plan the physical layout of package design interfaces, without the expenditure of time and dedication of resources required to perform traditional routing iterations. Route-planning allows package design teams to easily communicate with customers and other engineering teams to make intelligent trade-off decisions for layer usage, space allocation, Power Delivery Network (PDN) solutions, signal referencing and Die-to-Pkg netlist feasibility and optimization.

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