In this paper we present a new methodology that addresses the quality and reliability problems of applications that deploy “2.5D” packaging technology for integrated circuits (ICs). This technology employs through-silicon vias (TSVs), enabling greatly increased circuit density, performance, and functionality for a given volume. The 2.5D ICs require the use of an interposer to route signals between the chips and the package substrate. While this packaging solution has some distinct advantages over other packaging/mounting technologies, there are disadvantages as well. Qualifying and testing such connections is very difficult and expensive, and techniques for anticipating failure do not currently exist. Therefore, confidence in the reliability of 2.5D IC interconnects is lacking. Systems that use them may require a high level of preventive maintenance whenever possible, or such packaging may simply be avoided when such maintenance is not possible or practical.

The paper outlines an approach that combines embedded digital and analog measurement instruments that are capable of detecting and identifying opens and shorts in 2.5D IC TSV stacks. The monitors reside on the silicon interposer. This system is the first to address the difficult issue of 2.5D IC package interconnect integrity after assembly is done and when the related devices are deployed in larger systems. The innovation will improve reliability of TSV-based packaging by detecting and identifying faulty connections at package test during the manufacturing process. It also provides prognostic monitoring so that interconnect-related operational faults can be detected before actual system failure occurs after the packaged component is deployed in the field.

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