FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness.

The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced eWLB FO-WLP technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations.

This paper reports developments that extend multi-die and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize integrated packaging solutions for network, mobile products including IoT and wearable electronics. The test vehicles have ranged from ~30mm2 to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including 3D vertical interconnect, laser ablation, RDL processes and mechanical reliability characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on multi-die and 3D eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

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