With LSI micro-fabrication technology reaching its scaling limits, miniaturizing LSIs based on Moore's Law is unable to satisfy the CPU/memory module performance for high-speed, low-power, high-end servers, an alternative integration technology such as three-dimensional integration (3DI) is becoming mainstream. With the development of 3D stacked high-performance processors, specifications that excel in power consumption (200 to 300 W), heat generation, number of electrodes and large die area are required, necessitating a major technical leap from the conventional 3D packaging technologies. A guarantee of reliability and the yield loss is very severe, because of the high-performance processor's needing 30 times or more the both die area and the number of pins compared with the combinational high band width memory stacking.

We were the first to verify 3D logic device operation by integrating the following technologies: through-silicon via (TSV) technologies, in which signals are connected in the shortest distance between a top and bottom stacked ultra-large die area processor die; novel redundancy signal transmission design technology; super multi-pins connection technology for high-yield signal transmission with high bandwidth; and high reliability solder joint materials considering power integrity (PI) between stacked dies.

To achieve the high-yield TSV connection, the TSV redundant circuit was designed and installed into the stack dies due to the difficulty of the avoidance of defect density (D0) increasing such as large die area. Novel logic macro design with one redundant TSV for 16 signal node enabled the accurate switching selection to redundant defective TSV by using the execution of a pre-test sequence to find bad TSV. In addition, a redundant logic circuit of top and bottom interconnect is a design that gives control signal the redundancy. As a result, the higher operation guarantee was given to the operation execution of controlling circuit. This redundant circuit design technology demonstrated without yield loss of TSV interconnect.

For high-reliability fine pitch bump (40-μm pitch) and 10-μm TSV interconnect formation technologies, a large-current, high-heat dissipation and high-precision stacking technology were required. We have developed a process technology for fine-pitch micro bump junctions supporting large current and high-precision I/O bumps stacking dies with 200,000 or more pins using by Ni-Sn intermetallic compound (IMC) solder materials. We also have developed a high accuracy of large die stacking process to be used in fine TSV in which large amounts of current flow and connection terminal sections on dies, achieving stable supply of 300-Watt-class power consumption. Compared with the current density for a 10-year guaranteed lifetime, the case of IMC alloy joining achieves a current density resistance of 4 times more than that of conventional Sn-Ag solder materials, and this has proven to be effective for a high-performance processor.

By developing 3DLSI packaging technology compatible with ultra large dies for a high-performance processor and overcoming the issue of yield and reliability, we have achieved a redundancy design technology and micro bump materials of high-yield at product level stacked logic processor with over 750 mm square as full reticle shot size. In this paper, we will discuss the important key redundancy TSV design method and micro bump material technologies; in 3D packaging technology for realizing high-performance ultra large scale processor.

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