Over the last few years quite significant and well publicized advancements have been made in the IC industry in the potential adoption of fan out wafer level package platforms for both analog and digital applications. HD-FO platforms are likely to find significant adoption in the mobility, consumer application space as these have the capability to achieve sub-micron package routing density, high processor/memory and interconnect band width, very thin package height and small foot print area. Development of HD-FO package development reported in this work includes:

  • Multiple advanced silicon technology nodes

  • Broad range of package sizes

  • Single die, multi-die packages

  • Different package configurations that include with substrate, without substrate, organic and inorganic package redistribution layer options

  • System in Package (SiP) for RF applications

An electrical simulation based lateral and vertical interconnect insertion loss comparison is being reported for high density fan out packages and silicon interposer with through silicon via (TSV). Multiple metal layers, interconnect widths, organic and inorganic redistribution layers are modelled. High density fan out package provides orders of magnitude less vertical interconnect loss in comparison to TSV. Least lateral interconnect insertion loss is demonstrated by organic interconnect based HDFO package. For RF applications HDFO package based inductors of 1.1nH and 3.3nH demonstrate ~ 3 X improvements in Qmax when compared to similar CMOS based inductors.

In addition to providing differentiating technology value propositions through the advanced HD-FO packaging platform collaborative ecosystem, customer centric business model and flexible supply chains are also being built to meet the business requirements for the integrated circuit customers. Finally, silicon/package co-design environment and RF enablement will ensure that customers realize the benefits of seamless product design, fast yield feedback and reduced time to market.

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