Die placement accuracy requirements for fan-out wafer level packaging vary widely based on the process flow selected. Each process flow has attributes that define the challenges and requirements for die placement accuracy. Different fan-out process flows can require die placement to be done face-up or face-down. Alignment schemes for die placement can include global alignment, local alignment or a combination of both methods. Heat may be required for the carrier or die and placement force must be carefully controlled. Predictable placement of die prior to reconstitution is a key enabling technology for advanced fan-out products requiring fine line and space redistribution layers but it has the potential to improve yield in any of the fan-out processes. Accuracy requirements are driven by the photolithography done after reconstitution. Steppers are used with the assumption die to die spacing is repeatable within a given field area, however die spacing will inevitably be somewhat irregular due normal process variation in the placement and reconstitution processes. This variability can be reduced with the proper selection of placement equipment and molding materials. Die placement accuracy in conjunction with die shift from the reconstitution process must accommodate the design rules for RDL via size, passivation opening size and pad pitch for the intended devices. Die placement equipment selection is important since equipment optimized for accuracy may not have the highest UPH. The trade-off between speed and accuracy should be considered in the selection of the process to ensure the final product can be produced with the most competitive cost. It is important for manufacturers of fan-out products to understand the interaction of these factors in the selection and optimization of their fan-out process flows since the choice of the process flow imposes constraints that affect the final cost of the die placement process. This presentation will examine the critical factors influencing die placement accuracy for each of the three standard process flows as well as the methodologies that can be used to optimize UPH to achieve the lowest unit cost for fan-out products.
Face Down Die First Process Flow Requirements
Face-down, die-first process flows used for eWLB and similar processes represent the highest volume and most widely used group of fan-out technologies in production today. This process group places the die face down onto an adhesive surface prior to the reconstitution process and may achieve high yield for the intended products with a placement accuracy just under 10 microns. The carrier in use today is round and carrier diameter may slightly exceed 300mm. The process flow is a good choice for IoT and SiP low cost products and will probably be the first fan-out process to scale to panel. The key requirements for placement in this process include; very high speed, face down placement, no die heat, no carrier heat and low placement force. Global alignment schemes are used to place the die onto a carrier without local fiducials. Typical products are lower I/O count devices including Baseband, Power Management, RF, Analog and Bluetooth and the capability for passive placement is useful to enable some SiP and IoT products. UPH of the placement process is the key attribute for this process flow to enable cost reduction and a UPH of more than 10K is desired for a competitive process. Although the flow is most commonly used for single die products, it can also be used for multi-die products with a few products requiring higher placement accuracy extending down to 3–5um.
Face Up Process Flow Requirements
Face up process flows are used for TSMC InFO and similar processes. These process flows can be used for high value die requiring fine line and space and pad pitch. The process flow can support both 2.5D and 3D process options and has recently received much attention for its use in packaging Apple A10 processors. There are several variations of the process from different suppliers that combine carrier or die heat up to 150C and force up to 100N. 2.5D versions of this process flow typically use global alignment schemes whereas 3D versions of the process flow create an RDL layer and Cu pillars prior to die placement and may require local alignment. High accuracy placement is used for all versions of the process flow and accuracy requirements of 3um are typical. Round carriers are used with a standard diameter of 300mm. The process flow is well suited for high value die requiring fine pitch and multi-level RDL. The key requirements for this process include; high accuracy, moderate speed, face up placement, die and/or carrier heat and controlled placement force up to 100N. Typical products have higher I/O counts and can include Application Processors, Memory or Multi-die Si Partitioning. Accuracy of the placement process is a key attribute to ensure high yield and UPH of 4–6K is possible.
Face Down RDL First Process Flow Requirements
Face-down, RDL first process flows used for Amkor's SWIFT and similar processes represent the most recent addition to the portfolio of fan-out process flows. It is a unique process in that it uses a conventional Cu pillar bump structure formed on the die prior to the fan-out process. This process flow places the die face down on a pre-formed redistribution layer and uses either a local or mass reflow process to form the required interconnect metallurgy. Underfill is used prior to reconstitution to secure the die position and protect the interface. Round carriers are used today with a standard diameter of 300mm. The process flow is a good choice for high value die requiring fine pitch and multi-level RDL with high yield. The key requirements for this process include; high accuracy, moderate speed, face down placement, flux dip, low die heat, low carrier heat and low placement force. Local alignment schemes are used to accurately place the die on a carrier with 3–5um accuracy. The process is well suited for high value die or high density interconnect multi-die products. Typical products have higher I/O counts and can include Application Processors, Memory or Multi-die Si Partitioning. Accuracy of the placement process is the key attribute to ensure high yield and UPH of 4–6K are typical.
