For the next generation of 3D-IC applications, glass offers many desirable properties that make it an ideal interposer. In order to realize these applications, it becomes necessary to be able to deposit a Cu layer on both surfaces as well as in the glass via. In this paper we will present results of interposers that have fine line circuitry on both sides of the glass and have through glass vias (TGVs). One major challenge is how to create a TGV using either electrically conductive adhesives (ECAs) or Cu plating methods to achieve a high conductivity and reliable via connection.
Most work to date uses ECA materials to fill the TGV, however, many of these ECA materials have limitations in that they cannot withstand temperatures in excess of 400°C, are not hermetic and do not have the electrical properties of bulk Cu. In the first phase of our work, we have evaluated different commercially available ECA materials to fill the glass vias. A major challenge in using these materials is how to effectively fill the vias. Our test vehicle has a TGV with dimensions of 50um diameter and a 300um thickness on 2″ × 2″ glass substrate. A positive pressure screen printing process was used to fill the vias. These ECA materials exhibited a very high viscosity, due to the high Cu metal filler content, which made them very difficult to fill. Different pressures, squeegee speeds, and standoff conditions were evaluated to arrive at an optimized process to effectively fill the glass vias. A tilted X-ray inspection approach was used to characterize the yield for ECA hole fill. A DOE of different sintering conditions was conducted to determine how to maximize the electrically conductivity of the paste. From this work we will show the impact of sintering conditions on electrical conductivity and hermeticity.
In parallel, we have developed a process to Cu plate a TGV. In this approach, a dry deposition process was used to produce a conductive seed layer in the via having a diameter of 100um and a total substrate thickness of 300um. We proceeded to use a Cu electroplating process to plate up a conformal Cu layer in the glass via. In this work we have pattern plated circuitry on both surfaces along with the via to produce a glass interposer.
In addition, we were able to deposit a very thin layer of Si3N4 between two thick Cu metal layers on the topside of a glass interposer to produce a capacitor. The success of plating a TGV also enables the formation of inductors in a glass substrate. An organic dielectric layer using an Ajinomoto Buildup Film (ABF) was used to create a single buildup layer on the glass interposer. The combination of these individual technologies allows the capability to manufacture a glass interposer for advanced packaging applications. A discussion of the challenges associated in building glass interposers will be presented, which will include examples of recent builds of a double-sided Cu circuitry glass interposer and a diplexer module having Cu MIM (metal-insulator-metal) capacitors and inductors for RF applications.