Abstract
High temperature Silicon Carbide (SiC) integrated circuit (IC) processes have enabled devices that operate at >450°C for more than a year. These results have established the need for more advanced and practical packaging strategies. Off the shelf state of the art packages cannot withstand the same high temperatures as the semiconductor can for long periods of time. Packaging SiC die to survive temperatures >450°C, while also maintaining a reasonable packaging strategy that is agile, rapid, and modular, presents new challenges.
Presented is a technique for packaging SiC die with a focus on additive manufacturing, modular design scaling, and rugged survivability. This packaging strategy utilizes state of the art Additive Manufacturing (AM) methods, using an nScrypt 3Dn-Tabletop printer, together with stereolithography (SLA) digital light processing (DLP) 3D printing. Ultra-violet (UV) curable ceramic resins are used to create high temperature connectors. A design environment is also described, in which first time correct, interconnect layers are verified in software to reduce the risk of errors. A Ceramic Wiring Board Process Design Kit (CWBPDK) allows the design of single or multiple layers of metal, with fabricated SiC die. This interconnect is verified with standard design rule checking (DRC) and layout vs. schematic (LVS) software. Entire systems in packages can be verified using multiple SiC die. Input and output pins (I/O) are connected to these modules using metal connectors. After design, manufacturing can be performed in just a few days.
A system in package for driving a stepper motor was designed and fabricated using this packaging method. The motor actuator design utilizes four separate SiC die. These die contain large JFETs designed for sourcing current in a unipolar stepper motor architecture. This module was placed in a furnace at 470°C and demonstrated functional operation for over 1000 hours. These devices were able to source an average of 30 mA in >400°C temperatures to drive the room temperature stepper motor. A high I/O count, next generation package for discrete SiC chips was also designed using this packaging system. A single large JFET component was soaked for over 100 hours at both 500°C and 800°C. Utilizing Ozark IC’s automated test design environment, several DC and transient variables were captured for both tests and will be presented.
