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Analog and Logic High Temperature Integrated Circuits Based on Enhancement Mode Planar SiC JFETs
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) (2018) 2018 (HiTEC): 000079–000085.
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Normally-off 400 °C Operation of n- and p-JFETs With a Side-Gate Structure Fabricated by Ion Implantation Into a High-Purity Semi-Insulating SiC Substrate
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- M. Kaneko
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IEEE Electron Device Letters (2019) 40 (6): 866.