The stacked substrate packaging technology is a new 3D power loop structure utilizing multiple layer DBC to achieve ultra-low parasitic for the fast switching SiC device. This structure has a different geometry on interconnection between chips and substrate contrasting to the conventional module design, which needs optimization on the interconnection for the reliability consideration of this new structure. Analytical models of different bonding wire shapes and DBC structures were developed to calculate the von-mise stress on each model under thermal cycling simulation. The simulation results show that the stress on bonding wire reaches minimum when welding point located at the center of the top DBC substrate and the stress decreases when DBC top copper layer thickness increases or ceramic layer thickness decreases. Moreover, bonding wires with smaller diameter, certain peak height and width show lower stress and strain. Furthermore, thermal cycling tests were done on samples with same geometries of analytical models, and the wire pull test results showed consistency with the stress calculation results which verifying the optimum wire shape and DBC structure for the stacked substrate packaging.

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