IC technology, which has traditionally been dominated by dimensional scaling, is facing several technical and economic hurdles as it moves forward. Low K insulation has not been able to meet performance projections, copper traces are becoming more and more resistive, clock rates have been constrained due to thermal issues and multicore processors are demanding major increases in bandwidth and decreases in latency. Economic constraints will also begin limiting the number of IC companies able to develop leading-edge IC designs. Moving past 45 nm digital CMOS scaling will no longer guarantee lower cost and higher performance. All of these issues have crated a “perfect storm scenario” for the widespread adoption of 3D IC technology.

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