Mechanical reliability issues in electronic packages have drawn significant attention in semiconductor industry for decades and have increased product development cost significantly. Recent rapid growth of various portable electronic devices like smartphone and smartbook with increasing demand for more functionality in tighter space further challenges the limit of mechanical reliability. To reduce the product development cost and time-to-market, mechanical simulation has been extensively employed in semiconductor industry for the purpose of design optimization and reliability assessment. The importance of having the correct simulation methodology can't be overemphasized considering the extent of its utilization throughout the product development cycle. In this paper, we will discuss three fundamental mechanical modeling methodologies that are widely used for simulating flip-chip overmolded packages. These approaches are generally used to simulate package warpage at End-of-Line (EOL) as well as to assess package reliability from a stress point of view. The first approach we studied in this paper is to assume that the package is initially stress-free at a given uniform temperature, which is usually taken to be the peak temperature of the mold cure profile. However, this differs from the actual assembly process where package composition and cure profiles are different at each assembly processing step. The second approach simply accounts for that fact and assigns different stress-free temperature to each individual package component. For example, the die is assumed to be stress-free at the chip attach temperature and substrate is assumed to be stress-free instead at the substrate baking temperature. This approach captures more physics compared to the first approach. The last approach explores that idea further by simulating the actual assembly process, step by step, through element removal and addition techniques available in the software. Such study is also carried out for a flip-chip overmolded package with Through-Silicon-Stacking (TSS) technology. Both Die-to-Die-first (D2D) and Die-to-Substrate-first (D2S) processes are examined. Simulated warpage, as well as reliability assessment regarding different failure mechanisms using these three modeling methodologies are discussed in detail. The paper is prepared to the best knowledge of authors and those statements do not necessarily reflect opinions of Qualcomm Inc. Some data shared in this paper is normalized such that no commercial confidential information is published.

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