A key driver for 3-D device integration has been through-silicon via (TSV) technology that enables through-chip communication between vertically integrated layers. The TSVs typically have an electrical isolation using a dielectric layer between the silicon and the interconnect metal (e.g., copper). Recently, polymers have been proposed for use as the dielectric isolation layer, and polymers have been shown to increase device reliability by reducing “copper pumping,' where copper pops out from the TSV holes during thermal cycling. Traditionally, spinor spray-coating techniques have been used to fill TSVs with polymer material. However, using those techniques to fill and planarize very deep trenches (∼ 400 μm) and high-aspect-ratio structures has many limitations and usually results in voids, nonplanar surfaces, and lack of polymer flow to the requisite depths. Here, we present a novel process and a tool to completely fill and planarize deep trenches with a polymeric material. We use a combination of a traditional spin-coating process together with a physical planarization and fill process using the contact planarization tool to evacuate the trenches or vias on the wafer and then force the polymeric material inside the features. Using this process, we successfully filled and planarized trenches and vias 180 μm deep with 50-μm wide patterns as well as 400-μm deep trenches with ∼ 400-μm wide patterns. Initial results show complete filling and planarization of the material in the trenches without any voids.

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