Abstract
A novel 3D packaging technology of substrate-based platform – double side module is introduced in this paper. This technology is capable of integrating RF front-end module with the advantage of package size reduction, excellent warpage control, and enhanced reliability.
System in Package allows system designers to differentiate their products from others by integrating more functions to meet markets' requirement. It can also reduce the complexity of HW design while meeting their device / system requirements. The RF SiP is inherently heterogeneous integrated, for the foundry technologies of the dice inside could include digital CMOS, RF CMOS, III-V, piezoelectric, and other. In the era of 5G, new frequency bands of connected devices and denser component population have led to a demand for aggressive size reduction of RF FEM packaging solutions with good reliabilities and thermal management. The highly integrated 5G (under 6GHz) modem and RF FEM structure are crucial for modern premium tier smart phones' success, and are always a big challenge in the packaging industry due to its highly requirement of performance and manufacture yield.
I. Introduction
The coming of the 5G communication and the rapid growth of mobile communication device shipment motivates many innovations of the structures of the RF front-end module (FEM) in recent years [1]. One the one hand, the form factors of consumer communication devices, especially those of smart phones, still remain optimized for man-machine interface (e.g. display size, thin and light weight), the computing power, and operating time, while the number of operating frequency band combinations of such devices has been exploding. One of the most critical challenges is to miniaturize the RF FEM size, while maintaining the highest standard of performance required by both user experience and field operation. In order to achieve the desired RF performance of a front-end design, proper shielding and low insertion loss solutions are critical for the RF FEM implementation. In addition, the components used in the RF FEM are heterogeneous in their natures, and heterogeneous integration of dice from many different foundry technologies (e.g. digital CMOS, RF CMOS, GaAs, SAW, etc) is needed [2].
In recent years, newly developed System-in-Package (SiP) technologies are implemented on RF FEM to overcome these challenges. However, many practical mechanical and electrical considerations have to be taken into account.
II. Overview
For many years, 3D SiP structures have been proposed for digital circuit implementation [3][4], especially on the integration of application processor and memories, i.e., package on package (POP) structures. This approach is very effective in area reduction at the cost of height increases. Although the height can be reduced by dice grinding, however, when one tries to apply these approaches to RF applications, several key criteria need to be further considered.
First of all, often the RF circuitry needs extensive tuning for impedance matching, and configures to the RF bands and modes combination to fit to the operators' requirements where the devices are used. Moreover, the flow of the RF signals has to be streamlined in such as way that RF signal integrity and isolation among signals are maintained. As a result, in many cases additional shielding has to be built inside the package structure to achieve the desired performance. On top of that, when putting all the components and process from SiP tool box together, the module has to meet stringent warpage, thermal, and reliability requirement for the RF applications. Last but not least, the volume and market of the RF applications often requires very low cost and scalability in manufacturing that can meet the market demand.
In this paper, various 3D SiP double side module (DSM) structures are proposed to meet all these requirements. The very matured approaches of WLCSP, SMT, and die-bond wire-bond on substrate are used in this structure. Digital control signals are mostly on the lower side of the DSM, so that the signal integrity is maintained. The RF circuit, on the other hand, is mostly on the upper side, and their impedance control is achieved by proper substrate layers and layout. This partition allows for co-design of the packaging and RF performance easily. The overall size reduction in all XY and Z directions, as well as overall cost mitigation, can be achieved by carefully selecting the right approaches of the DSM implementation.
III. Result
Figure 1 shows the cross section view of various types of DSM solutions. On the top side of the module, the components can be either molded (as shown) or open top. When it is open top, this structure is called double side assembly (DSA) in many cases. A shielding can be applied on the top layer either by conformal coating in the case of DSM, or simply by placing a metal can in the case of DSA.
The top side is a good location for placing the RF components for the ease of tuning and frequency band configuration. The active components and large digital dice are usually placed in the central area on the bottom side, while the pin-out connections are around the peripheral of the module. The connections can be implemented by various ways. In the figures there are solder balls, copper or solder pillars, interposer/frame boards, and copper balls. There are pros and cons in terms of their mechanical properties for each of the connection types, and the designers should choose carefully at the beginning of the design cycle. It is often desired the lower side to be as thin as possible. It allows shorter vertical connection length, and hence lower loss and denser in both pitch and diameters of the connections. As a result, dice that are grounded to the desired thickness and passive components of low profiles are often used on the lower side.
The advantage of area reduction can be easily recognized in Figure 1, when compared to a single side module. We use a WiFi module whose original design has dimension of 11.7*8.9*0.8 mm^3 (L*W*h) as a demonstration. When placed in DSM, the dimension is reduced to 9.6*8.6*1.06 mm3, where 20% area reduction is achieved. The thickness is increased from 0.8mm to 1.06mm, however. There are two reasons can contribute to the thickness increase. One is the thickness of the lower side, and the other is the number of layers of the substrate. In order to compensate for the numbers of substrate layers used in DSM, a coreless thin substrate is used for the design. The cross section view and information of the stack-up are shown in Figure 2 and Table 1. However, if bare die is used, rather than packaged component, the thickness won't be as large.
The use of the connection type is important to the control of the thickness of the lower side. In the first example, we used copper ball for the connections. It is better in height control after reflow, and is easy to implement. The cross section view is shown in Figure 3. It is found the copper ball remains in round shape with good connection after the ball is implemented on the substrate.
The warpage simulation of such a structure is shown in Figure 4. The simulation gives good result for a module of this size.
This DSM module is further put under reliability test, and the test items and conditions are shown in Table 2. The WiFi DSM module passed the reliability test without any failure.
If further height reduction is desired, one can thin down the WiFi baseband controller before it is applied on the lower side of the DSM, and use copper balls of smaller diameter. It is expected that when such a method is applied, together with using low profile components for the highest ones both on both upper side and lower side of the DSM, the height increase can be offset and mitigated with reasonable cost.
Another example of 3D SiP using DSM for RF FEM applications is done with solder balls and wire-bonded controller on the lower side. The cross section view and thickness dimensions are shown in Figure 5.
Since the requirement of area reduction of this DSM is aggressive, two rings of connection balls are used on peripheral to allow for the desired numbers of connection while maintaining the area within spec. The RF module interface controller on the lower side is thinned down to around 150um, and low profile wire bonding techniques are used for connecting it to the substrate. Together with use of solder balls, the cost of this DSM for implementing the lower side is greatly reduced. The cross section of the 2nd DSM example is shown in Figure 6.
After the solder ball is attached and molding applied to the lower side of the DSM, one additional process step of laser ablation is applied to expose the solder balls. The result shows good solder ball exposure in XY and Z directions, good shape maintenance, and good attachment to the substrate after the ablation.
The cross section view of the 2nd DSM example with wire-bond applied to the interface controller on the lower side is shown in Figure 7.
The height of die bond, die thickness, wire bond loop, and over molding is shown in Figure 7. It allows the overall thickness on the lower side to be less than 0.3mm, hence small size of solder balls can be used for connections. The resulting connection ball pitch and diameter is typical for normal PCBA SMT reflow conditions. The overall improvement of lower side implementation of DSM not only mitigate the DSM height, but also reduced the implementation cost, that are critical for the market requirement of the RF front-end module applications.
IV. Conclusion
A novel 3D SiP approach of implementing double side module is proposed, manufactured, and measured in this paper. It is demonstrated that this structure is ideal for implementing heterogeneous integration of components from various foundry and packaging technologies. The applications include RF front-end module and modem module that are important for the 5G era.
Two examples of DSM are built and result shown in this paper. It is found that not only the XY area is greatly reduced, but also the overall thickness and cost can be optimized in carefully selecting the right process technologies. The DSM example also shows good warpage and reliability.
Acknowledgment
The authors of the paper would like to thank ASE Material for manufacturing of the coreless substrates, and providing the cross section views and stack-up information.
