Flip chip reliability and intermetallic compounds for SIP module

In the aeronautical field, electronic integration roadmaps show that the weight and the volume of on-board electronics must be reduced for the most recurrent functions in the next few years.

In this way higher level of integration and heterogeneous technologies are being developed today. To reach this goal components and assemblies need to evolve. Increasingly, the choice is made to use unpackaged chips in order to gain in flexibility for implementing 3D architectures at the assembly level in particular with system in package (SIP) concept. At the same time the overall reliability needs to be further improved.

It is in this direction that our work is carried out, particularly for ASICs accompanying MEMS sensors or for reducing the footprint of the cards used for calculators.

The transition from 2D to 3D has gone through the migration from a System on Chip (SoC) approach to a System in Package (SiP) architecture of the electronic components. As a first step 2.5 D has been introduced where the components are mounted on an interposer allowing them to be connected one to each other side by side and then connected to the board through fan-out redistribution layers and TSV. 3D is conceivable only when a component is mounted on another with through silicon via (TSV). Multiple assemblies are then possible with the use of μbumps and TSVs and embedded dies in the packaging substrates is increasingly used to enhance the compactness of the systems while increasing its performances.

Firstly, all these architectures are developed in order to reduce the footprint of the rooting surface, which in all fields of application is a major issue [1].

Secondly, 3D interconnections like TSVs and μbumps implemented at chip level decrease the distance between components. These configurations improve the speeds in the connections and thus the overall performance [2].

Flip-chip assembly is one of the most important features for these types of packaging. Traditional wirebonding shows limitation in the number of pins while for the same number of pins, flip chip technology authorizes having a chip with area 50% smaller [3].

The democratization in using copper-pillar, underfill and encapsulation participate in the adoption of flip-chip [4]. Practically these types of assembly need fine pitch organic substrates and μbumps which are the focus of this work.

Copper-pillar technology is used for a long time for flip-chip assembly. System miniaturization using copper-pillar is already in many products. For example manufacturers like Flextronics or INTEL have fine pitch copper-pillars in their products [5], [6], [7]. Nevertheless, in the aeronautical field it is not fully adopted because of reliability concerns.

Today, μpillars with pitch of 10μm [8] exist, but not for flip chip assembly on organic substrate. Current publications show pitch below 30μm but this is only on silicon substrate, where CTE mismatch does not represent a limitation.

For organic substrates the state of the art gives more heterogeneous figures. Although a large majority is around 100 μm, assemblies with smaller pitches can be found like for example Siliconware Precision Industries with 70μm [9], IBM with 50μm [10], Institute of Microelectronics A*STAR with 30 μm pitch [11], or Amkor technology with 50 μm [12].

In works involving pitches of 50 μm or less, the use of the NCP technique is often present. For example thermal cycling reliability was successfully passed with copper-pillars of 30μm pitch and thermo-compression process on organic substrate with Cu bond pad [11]. However this NCP method seems to present some problems with fillers entrapment observed in interconnects when solder cap are small, as can be seen in [11]. This problem causes failures during thermal cycling because of cracks propagation.

This work reports new technological solutions to increase our ability to integrate more electronic components in a reduced volume. The aim is also to improve at the same time the overall system reliability.

As a general concept, SIP is composed by several active and passive components stacked on an interposer, additionally with embedded die technology, to reduce interconnection lengths. Both sides of the interposer can be used with flip-chip assemblies as describe on Figure 1.

This work focuses on a simple SIP test vehicle which includes the top die assembled by flip-chip with copper-pillars or gold-stud bump technologies on either an organic or a silicon interposer. The aim is to evaluate thermal cycling reliability and extract mechanical design rules from our test vehicle to help designing future functional SIP, this being in agreement with the needs of our laboratory.

Configuration of a flip chip assembly is represented in Figure 2:

The choice was made to produce the silicon chips at LETI, Grenoble. These are daisy-chained test vehicle silicon dies. Silicon test chips have different configurations:

• - Chip thicknesses (50, 100, 200 μm).

• - Chip sizes (square of 2, 4, 8 mm).

• - Bump size (25μm, 50μm, 65μm diameter).

• - Pitches of the bumps (50, 100, 150, 250 μm).

• - Number of interconnection rows (1, 2, array).

• - with/without redistribution layer (RDL).

These configurations are designed to obtain a large amount of information for defining future functional SIPs. For illustration, two configurations are presented in figures 3 and 4.

The conductor lines are made with sputtered aluminum metallization, with a mineral SiO₂/SiN passivation layer on top and a SiO₂ oxide layer underneath. This part constitutes the first routing level.

Organic substrates are LGA type of 15mm by 15mm in size. Each LGA will allow the flip chip stack of one test chip. The structure of the substrate is described in Figure 5.

It is composed by a central part called core (MCL-E-679FG (R)) and two outer layers called build-up (ABF-GZ41). The total thickness is about 1mm.

OSP (Organic Solderability Preservative) finishing was chosen because it is considered as the most adapted for fine pitch assembly [13], [9].

Copper-pillar bumps are made at CEA LETI. The structure is composed of a copper pillar which is grown by ECD (electrochemical deposition) on a titanium/copper/titanium seed layer. On the copper pillar, a layer of 2 μm of nickel is grown followed by a 96.5%Sn3.5%Ag solder layer to form the last part of the bumps. The Ni acts as a barrier against the interdiffusion of Cu and Sn and limits the growth of Cu₃Sn₅ and CuSn intermetallic compounds (IMC). After deposition, a first reflow is carried out at 260°C to obtain a hemispherical shape of the solder as shown on the Figure 6.

Assembly is made by mass reflow at CEA LETI on DATACON pick and place equipment. After dipping, chips are positioning one substrate copper pads and three reflow is carried out at 260°C to obtain final module.

Once the chips are assembled on the substrates, the next step is the underfilling process to fill the space between the chips and the substrate. This allows a thermomechanical reinforcement of the assembly that helps preventing failures.

NAMICS underfill material is used for this step.

Figure 7 represents the overall process flow describing the study. Electrical tests are performed at different levels of the flow to control the process and finally at different stages of the stress test.

ANSYS program was used to evaluate plastic strain energy of the flip-chip assembly. Stress is principally due to the CTE mismatch between the silicon chip and the receiving substrate. Three-dimensional solid elements with eight nodes were chosen for the finite element modeling. The mesh near the copper-pillar bump is chosen smaller than the other parts, to allow a convergence of the results. The mesh used to model the copper pillar bump interconnection is shown in Figure 8. In order to be realistic, the model is tested to ensure having the less dependency of the mesh but keeping time of processing at reasonable value.

The results were obtained using Anand law (1).

Equivalent plastic strain rate

A

constant with the same unit as the strain rate

Q

activation energy with unit of energy/volume

R

universal gas constant with unit of energy/volume/temperature

θ

absolute temperature

ξ

dimensionless scalar constant

s

internal state variable

m

dimensionless constant

We consider a perfect bump and a perfect contact interface with no void.

Chosen parameter is usually the per-cycle inelastic strain, called PLWK. It represents the behavior of solder when thermal cycling is performed on the package.

In order to have a criterion, the average of plastic strain energy (2) is used to obtain one value in each configuration:

Where ΔWave is the average inelastic strain energy density accumulated per cycle, ΔW the strain energy density accumulated per cycle for each element and V the volume of each element. Average plastic strain energy per cycle prevents mesh dependency due to geometrical edge effect [14], [15].

Thermo-mechanical parameters introduced in the model are described in table 1 and Table 2.

Elastic behavior properties are used for chip, substrate and copper. SnAg solder behavior is considered with a viscoplastic law as described previously. Parameters are extracting from papers [16] [17].

Study is focused on thermal cycling reliability. The choice for the temperature excursion according to our laboratory needs is fixed between −55 °C and +125°C.

In order to have the corresponding life time to failure prediction with experimental findings. Darveaux's law is used with the following equations. This model is based on the fact that failure starts in a solder from the edges to the center with a defined speed. Darveaux proposes in its model two terms to calculate the number of cycles to failure (Nf):

• - the number of cycles necessary to initiate the cracks (N0). This is a function of the cumulative energy density per cycle (ΔW_pl), ΔW_pl is extracted for the area 1 (solder) in the figure below representing the strain in the solder.

• - the propagation speed of the cracks in the solder (da/dN). K1, K2, K3, K4 are Darveaux's constants depending on the materials.

Experimental tests will be compared with finite element study essentially between the underfill (U) and the no underfill (NU) configurations as represented below (figure 10). Plastic strain energy per cycle is extracted like described in the previous part.

First, this simulation shows that there is a dramatic impact of the underfill on average plastic strain energy per cycles. For example, the strain energy per cycle is reduced by a factor of 18 with the presence of underfill for a chip of 4 mm.

Secondly, this simulation shows that there is a significant impact of the chip size with NU case. Logically, the energy density almost doubles each time that size of the chip double, directly related to the distance separating the bump to the center of the chip. Conversely, for the U configuration, underfill limits the impact of the size, linear increase of density energy is present but impact does not double with chip's size. The sensitivity of the chip size is then very low with only few % of increase when the size goes from 2 to 8 mm.

Moreover, the impact of the chip's thickness can be noted. In this simulation (Fig. 11) the thickness of the chips was changed between, 50 μm, 100 μm, 200 μm and 400 μm. For U configuration, impact between 50 μm and 200 μm chips is +30% whereas with NU configuration the impact is only +10%. There is no obvious explanation for this difference but it can be due to the limits of the model

Finally, for both cases (U and NU) the impact becomes not significant for a chip having a thickness greater than 200 μm. Indeed, the increase of energy density is almost zero for no underfill and 8% for underfill configuration when the thickness goes from 200μm to 400 μm chip.

In a second time simulations are performed on secondary order parameters. Indeed, in the case of the NU configuration which represents the most sensitive case, other parameters such as the number of rows of bumps, or the height of copper pillar can be some parameters influencing the plastic strain energy per cycle. Three configurations of copper pillar (cu-pi) height have been simulated: 10 μm, 60μm and 30μm (standard configuration). The table below shows the impact on energy density of each of these different configurations.

All these different cases will be tested experimentally. For the moment, simulations showed that underfill is from far the more influent parameter on the assembly life time followed by chip size. In other hand impact of RDL, numbers of row and copper height is low on life time.

In order to have the corresponding life time to failure prediction to be compared with experimental findings finite element model and Darveaux's laws are used for the different sizes of chip and reported in table 4.

Life time prediction based on Darveaux's law is around 50 cycles in the worst case in the NU configuration with 8 mm chip. On the other hand, in the best case, 27000 cycles are predicted with 2 mm underfilled chip. For 4 mm chips, prediction is around 200 cycles for NU configuration and 25000 for U configuration.

First experimental results show that, with 4 mm chip, failures for NU assemblies arrive before 100 cycles, in the opposite U assemblies pass at least 6000 cycles without failures and with no sign of degradation on daisy chain electrical resistance (see Figure 12). Thus, the numbers of cycles to failure is in good agreement with experimental findings for 4mm size chips.

With current Darveaux parameters, the number of cycles to failure prediction is likely higher than in reality. In the NU configuration it appears that assembly life time of 4 mm chips is already very critical and of 8 mm not viable.

EBSD allows characterizing the microstructure and the local crystallography of different materials like metals for instance. The information on crystallography leads to determine the phases of the materials, but also the global orientation of the grains and the local disorientation inside the crystal under study.

For our study other important points obtained from the EBSD analysis are the composition, the form factor and the size of the metallic grains constituting the copper pillars/bumps. The form factor is then the ratio between the small and the long length of each grain.

Figures 13, 14, 15 and 16 shows the EBSD analysis for the copper pillar interconnections in three different cases. The first represents initial assembly without thermal cycling. The aim of this configuration is in particular to have a reference. The second represents a NU stack that failed after 50 cycles and the third case is after 2000 thermal cycles in U configuration.

Case after initial assembly (Figure 13&14).

The EBSD analysis showed that there are four different metallic compounds Cu₆Sn₅, Cu₃Sn, Ni intermetallics and SnAg in the interconnect structure. For instance, in the chip's interface, we can observe the formation of an intermetallic (Ni_1-x,Cu_x)₆Sn₅. This has been confirmed thanks to the coupling with an EDX analysis.

We can also observe the presence of some silver precipitates (purple) in the tin solder. On the bottom side of the interconnection it is possible to see a very fine Cu₃Sn (blue) intermetallic represented in blue. The upper part of the copper pillars contains copper and also nickel. Having space groups close together, the EBSD does not differentiate them, therefore both have the same red color on this figure 13. In orange on both sides of the solder, at the interfaces with the copper and the nickel, an intermetallic Cu₆Sn₅ is formed. For each side of the interconnection, intermetallic has a very different shape, first because of the presence of the nickel layer on the chip side, which does not lead to the same intermetallic growing between copper and solder and second because of the different thermal histories seen by the two parts, one has seen one more reflow (top) due to the bumping process. It has been observed that in the case of a Sn-Cu solder and when a Ni layer is present, the product of the reaction is (Cu, Ni)₆Sn₅ at the interface [18].Instead, on the substrate side, the Cu₆Sn₅ phase is formed at the Cu-Sn interface. In a second step the Cu₃Sn phase is created at the Cu₆Sn₅-Cu interface. For their growth the activating temperature is different, below 80°C for the Cu₆Sn₅ phase formation, and higher to this temperature the growth of Cu₃Sn accompanies that of Cu₆Sn₅. [19].

When the stress is not present, solder present a uniform structure with bulk tin and intermetallic compounds at the interfaces with copper. For example in Fig 14 there are only two big grains in the solder. The thickness of Cu₆Sn₅ intermetallic is around 1.65 μm with a grain form factor close to 1.47 in the interface with the substrate and 1.1μm with form factor of 4 for the chip side.

The intermetallic grains form is quite long because recrystallization is not present at this step since it has just growth during the reflow of the stacking.

Case without underfill (Fig. 15)

After only 100 thermal cycles we have seen that stress is already a lot more important than with the underfill configuration with thousands of cycles. Solder joins present many grains of tin, the size in around 7 μm. In Fig 15 we can count as much as 33 individual grains of tin material. This recrystallization effect is clearly due to the stress applied in the structure since the phenomenon is not observed in the sample with underfill even after 2000 cycles. Crack propagation is in the middle of the tin layer, this is likely the least resistant location. In this case ductility of tin is not sufficient to relax stress without cracking. Start of the crack propagation is located at the solder mask corner.

The size of intermetallic compounds stays the same than in the T0 case. The thickness of intermetallic is around 1 μm with a form factor close to 1.6 close to the substrate and 1.7 close to the chip so the intermetallic grain form did not change. This can be explained by the short thermal loading seen by the sample after only 100 cycles.

It is often common to see breaks in the region of the copper/solder interface for larger structures. Here the crack is inside the solder, this central propagation is correlated with the simulations as shown in Figure 16 with the configuration without underfill, with and without a solder mask. This simulation fit well with the observation, indeed the stress is concentrated in the center of the bump and initiates at the corner of the solder mask even if the constraint values in the solder remain similar to a non-solder mask configuration.

Case with underfill after 2000 thermal cycles (Fig. 17)

The grain size is around 20 μm, an intermediate value between T0 and the NU case.

When stress is present (due to the difference between silicon and substrate CTE) and with an important number of cycles, the interconnection present more intermetallic compounds, their sizes are bigger than in the initial case. The thickness of the intermetallic layer is around 2 μm for each side with a form factor close to 1.3 close to the substrate and 1.6 close to the chip. The intermetallic grains form is rounder likely because of a recrystallization phenomenon and the long structure is dividing in many little rounded shape grains. In this case, 2 or 3 layers of intermetallic grains are present.

The main finding obtained from the EBSD study concerns the evolution of the solder structure under thermal stress. With the underfill sample and even after 2000 cycles the stress in the interconnection stays at a very low level as confirmed in the first part of this paper so the morphology of the solder does not change significantly nor any sign of crack initiation can be observed. Conversely, in the NU case we observe a dramatic change in the solder morphology with an important recrystallization phenomenon leading to the presence of small tin grains. Moreover, in this case a crack can be easily observed in the middle of the solder as evidenced by the electrical failure.

In addition, an evolution of the intermetallic compounds can be seen between the different configurations. The Cu₃Sn initially at 0.4 μm is measured at 0.3 μm after 2000 thermal cycling, since we are at the maximal resolution of the EBSD and he has no reasons of reduction of seize with thermal cycling. For the Cu₆Sn₅ compound an evolution from 1.65 μm to 2.08 μm equivalent to a growth of 20% of the intermetallic thickness after 2000 thermal cycles. This observation is in good agreement with the expectation since the loading temperature of the cycles corresponds to the metastable Cu₆Sn₅ phase growth rather than the higher activation energy Cu₃Sn phase growth.

The size of intermetallic compounds is finer with an average size of less than 0.5 μm for the Cu₃Sn phase and less than 2 μm for the Cu₆Sn₅ phase.

Grain does not have preferential orientations in any configuration.

Finally, a summary of intermetallic thickness measures is reported in the table 5:

In this paper, we present the design and the fabrication of a test vehicle having different configurations of interconnects dedicated to a reliability study of silicon die-to-substrate flip chip assembly. Chips with 2 mm, 4 mm, and 8 mm are used with several configurations of copper pillars-μbumps. For all those configurations organic and silicon substrates have been also designed and fabricated. The main objective is to study the behavior of the flip chip interconnects during thermal cycling between −55°C and +125°C. First, reliability results for an underfill and non underfill configurations are presented. Impact of underfill is clearly evidenced on experimental samples submitted to thermal cycling. In parallel, thermo-mechanical analysis by finite element modeling is performed to extract values of plastic strain energy per cycle and predict the failure mechanisms and the number of cycles to failure using Darveaux law. Correlation with first experimental trials proved the validity of this finite element model. First, the most critical parameters acting on thermal reliability are being determined. Secondly, evolution of the solder morphology with the +constrain on the μbumps are studied with EBSD analysis, this first analysis quantify also the evolution on the size and on the morphology of intermetallic compounds during cycling.

This study is made with the support of Kyocera who is providing the organic substrates. This project was supported by CEASARLab–SAFRAN/CEA joint laboratory, a special thanks to the research teams.