Unlocking the full Potential of Lithography for Advanced Packaging

Lithography entered the Back-End stage of electronic device manufacturing with the introduction of Flip-Chip packaging technology in the 1990's. This is often referred to as Advanced Packaging as opposed to traditional packaging in which the major technologies used are die placement, wire bonding and molding. The feature sizes used in Lithography for Advanced Packaging in the early days were larger than 10 micron, which allowed the use of contact/proximity aligners providing a cost effective patterning solution. Lithography was first used for gold and solder bumps. The solder bump processes included Redistribution Layers (RDL) connecting the original bond pads of the chip to the solder bumps, which are usually arranged in a grid array.

The performance of aligners, however, was soon pushed to their limits. One particular issue causing serious overlay errors was registration errors at the edge of the wafer caused by mask expansion due to mask heating. With the introduction of 300mm wafers, the issue became even worse. Because of these performance limitations, the Advanced Packaging industry started to explore alternatives. The solution was offered by steppers using projection Lithography, which allows for a much better performance in both imaging and overlay. At that time steppers were already widely used for wafer processing in Front-End fabs. Moore's law was already at full speed and had produced several generations of Lithography steppers with resolution capabilities ranging from microns down to a few hundred nanometers. Advanced Packaging started to use existing steppers with a resolution capability of 2 micron because these systems fulfilled a good part of the requirements in combination with a reasonable price. Imaging and overlay were more than sufficient and although throughput was not at the level of aligners it was still reasonable. Other requirements of Advanced Packaging were not fully supported by the available Lithography tools. However, since the demand for Back-End steppers was still low, it was not feasible to develop a stepper dedicated for Advanced Packaging applications. As a result, the Back-End industry took the misfit between Advanced Packaging requirements and what the older Front-End steppers offered for granted. Over time partial solutions became available for specific Advanced Packaging requirements. However, customers in many cases still had to use workarounds in order to be able to run their processes with the Lithography systems offered. Areas of concern include:

• Contamination control because of resist outgassing

• Flexibility in substrate handling, including different sizes, thicknesses and high degree of warpage

• Effective focusing/levelling over a wide range of photo resist thicknesses and high topography substrates

• Wafer Edge Exposure and Wafer Edge Protection to support single wafer cup-based plating processes

• Flexibility and adaptability for future requirements in the fast changing world of Advanced Packaging

In addition to that, many of the current Lithography systems in use for Advanced Packaging have designs that originate from many years ago and don't employ modern technology in areas like Mechatronics and Software. This is seriously impacting the ability to adapt these systems to future requirements for Advanced Packaging.

Kulicke & Soffa Liteq B.V. carefully analyzed the Lithography requirements for Advanced Packaging. First conclusion was that equipment currently offered only partially meets manufacturers' requirements. In addition to that there is a concern whether future requirements can still be incorporated in these systems, since the world of Advanced Packaging is changing rapidly. This is because solutions for the ever increasing need for further integration of functionality no longer only come from tighter resolution nodes in the Front-End based on Moore's law. In the past few years Advanced Packaging also made a significant contribution in offering solutions and this trend is rapidly moving forward, which will create new requirements for processes and equipment.

On the basis of this analysis, a Lithographic system was designed starting with the requirements of Advanced Packaging applications in mind. The result is a stepper that fulfils current Advanced Packaging requirements in the best possible way AND because of its flexible and modular design is also prepared for upcoming new requirements. Furthermore, the system is designed in such a way that upgrades and new options simply can be integrated. Fig. 1 shows the outline of the system. In response to the requirements the following development strategy was adopted:

• Proprietary designs for optics and metrology components to ensure best-in-class imaging, overlay and throughput

• Laser based light source providing overall low Cost of Ownership and scalable intensity and throughput

• State-of-the-art, proven and therefore reliable handling and stage technology available on the market providing fast wafer handling, and the capability to handle several wafer types (thin, thick, warped, etc.)

• Modular system architecture and building a competence in integration providing high flexibility, high extendibility and upgradability

• Model driven software design and proven industry standard user interface providing Ease-of-Use, fast upgradability and robustness

Kulicke & Soffa Liteq B.V. is strongly embedded in the high-tech region in the southern part of the Netherlands with many high tech companies. We share strong relations with these companies and institutions and leverage the expertise and supplier networks available. We have a strong relation with in particular, ASML, which used to have a share in the company until mid 2017. After that Liteq was acquired by Kulicke & Soffa and a Supplier Level Agreement was put in place to continue to assure the support from ASML technical experts for our development program

Packaging used to be only about cost effectiveness until the 1990's when speed and bandwidth of the final device started to become limited by technologies used in packaging. Therefore, next generation packages needed different ways of making interconnects with shorter path lengths and lower resistance and inductance. Flip-Chip was the first answer to this problem, using bumps and RDL for which Lithography was required. Flip-Chip not only offered higher speed but also smaller and thinner packages which became important for the growing mobile market. Now, 20 years after the introduction of Flip-Chip several other Advanced Packaging technologies are available.

Advanced Packaging grows in two ways. The first part is the growth of the semiconductor market as a whole in terms of the number of 300mm equivalent wafers processed in all Front-End fab's. By the end of this decade the total volume is forecasted to approach 100 million 300mm equivalent Front-End wafers per year [1]. All of these wafers will have to go through a packaging process, either Advanced Packaging or traditional packaging using wire bond. The second part is the increase of the fraction of wafers that go through an Advanced Packaging flow, which in the recent past rapidly grew to 30% and is now approaching 40% [1]. At this point in time the following Advanced Packaging technologies exist:

• Flip-Chip using solder bumps or copper pillars in combination with RDL. Copper pillars are replacing solder bumps because smaller pitches are possible

• Fan-In, which is extremely popular for mobile applications since it delivers small, thin and low cost packages. Fan-In does not use an interposer. Instead, big package balls, which connect the device to the PCB are put directly on the chip surface. An RDL in between connects the bond pads on the chip with the package ball grid array.

• Fan-Out is an extension of Fan-In. The original wafer is diced and reconstructed in new wafers where the die are embedded in epoxy with spaces between the die. In this way extra space is created to “Fan-Out” interconnect away from the chip. This allows to extend the Fan-In technology to die that have a higher I/O-count. Fan-Out is therefore an alternative for Flip-Chip for larger, more complex die. Fan-Out is a very versatile Packaging Platform with many advantages over Flip-Chip, which has been described in many publications [2].

• 3D-IC, which is a technology to stack die and wafers using Through Silicon Via's (TSV's). Many of the 3DIC processes are fully implemented in Front-End fab's

• 2.5D-IC, which is using silicon interposers with fine pitch and TSV's to combine several chips into one device

In publications and forecasts, Fan-Out has been put forward as the promise towards the future with double digit growth numbers [3]. This is because it is a very versatile packaging technology supporting small and thin packages with good electrical and thermal characteristics. Moreover, it supports heterogeneous integration. Forecasts for Fan-Out still vary a lot year after year, but the common opinion is that Fan-Out will be the most important driver for growth in Advanced Packaging [3].

It is important to note that Fan-Out competes with Flip-Chip. The interconnect functionality of the Flip-Chip interposer is transferred to the Fan-Out RDL stack. One of the promises of Fan-Out lies in the fact that the RDL stack supports tighter resolutions in comparison to the Flip-Chip interposer and therefore allows for a denser interconnect. The tighter resolutions used in the RDL Fan-Out can be manufactured with Lithography systems such as the LITEQ 500. Therefore, with the growth of Fan-Out the market for systems like the LITEQ 500 is also expected to grow.

From the above it is clear that the requirements for state-of-the-art Lithographic steppers will to a large extent be dictated by what Fan-Out needs. The LITEQ 500 system is tailored to fulfill these requirements and because of the modular and flexible architecture it will also enable future requirements.

• Resolution and Depth of Focus: The system is qualified for a resolution of 2 μm Lines and Spaces although 1.5μm is attainable. The usable Depth of Focus @ 2 μmL/S is more than 15 μm across the entire exposure field. The system uses a narrow band single wavelength laseras the light source. This allows for low aberrations as thelens design takes advantage of the single wavelength.

  The application of Field-by-Field focusing with a highrepeatability further helps to optimize the usable Depthof Focus. In addition to that, Field-by-Field tiltcorrections are possible to support processing of waferswith high topography and high warpage.

  Dose repeatability is optimized using a closed loopcontrol system, resulting in a performance below 1%.

  To address the upcoming requirement for finerresolutions a lens is being developed with < 1 μmresolution capability.

• Overlay: The system uses pattern recognition alignment. The design of the alignment camera supports the full employment of sub-pixel capabilities of the state-of-theart image processing software. Lens magnification control is available to optimize Intra-Field overlay. The performance is better than 500nm Matched Machine Overlay relative to any other LITEQ system. The software supports advanced overlay schemes using higher number of marks to better correct for local variations. Die shift maps, measured on suitable metrology systems can be imported to achieve optimal overlay on reconstructed wafers.

  For 3DIC applications, backside alignment using InfraRed is possible.

• Throughput: The 60W laser, which comes standard with the system delivers a 95 wafer/hr raw throughput at 400 mJ/cm² dose, which is amongst the highest in the industry. For low volume environments the system can be delivered with a lower power laser, which enables to further reduce cost.

  Mercury lamps are at the end of their development cycle. Lasers, on the other hand are still in the early phase of their life cycle and there is a lot of innovation in areas like power, higher Watt/$, longer lifetime and lower maintenance costs. The LITEQ systems take full advantage of these developments in the current and future generations. Additional advantages of lasers are their stable power level over time and the environmental friendly nature compared to Mercury lamps. It has already been mentioned above that the single wavelength of the laser light allows for a simple and therefore affordable lens design, which drives down the overall system cost.

• Reticle Masking (REMA): There are many situations with complex wafer layouts, which e.g. include fiducial alignment marks for other process steps in the AP flow, wafer-ID exclusions or process control modules. Many of the currently available systems use multiple fields on the reticle to support this. The big disadvantage there is the need to move and re-align the reticle when shifting to a different reticle field, which may take up to tens of seconds, reducing throughput. The LITEQ system uses reticle masking blades near the reticle, which is a fast and flexible solution to select any rectangular area on the retical without the need to move and re-align the reticle. Refer to section IV-c for more detail on the reticle masking.

• Contamination Control: the combination of thick resists and high doses often results in resist outgassing, which contaminates optical surfaces, which negatively impacts transmission and throughput as well as imaging performance. The system includes several measures to deal with contamination. The large working distance of 20 mm between lens and substrate results in a low level of optics contamination to start with. For excessive outgassing an extraction hood is placed between lens and substrate. In addition to that, a removable and cleanable bottom lens element is in place. This allows for cleaning in an easy and safe way without the risk of damaging expensive optics.

  The inside of the lens is constantly purged with inert gas to remove any possible contamination.

• Substrate Handling: A large variety of substrates can be handled by the system, both in size, thickness and material. In particular, for the handling of warped wafers the system offers a large degree of flexibility; warpage levels of more than 6 mm can be handled.

• Wafer Edge Processing is required to support single wafer cup-based plating. This functionality includes both Edge Bead Removal to allow electrical contact with metal seed layers and the creation of a resist seal ring within the Edge Bead to seal the volume within the plating cup. The SW controlled Wafer Edge Protection provides a large degree of flexibility in selecting the desired pattern diameter. There is no contact between masking blade and resist, which prevents contamination. The distance of the masking blade to the resist is tightly controlled resulting in good resist sidewall uniformity. Last but not least, there is negligible impact on throughput.

  Wafer Edge Exposure is also fully integrated in the system and utilizes the light of the laser source, hence no additional mercury lamp is needed and this further lowers maintenance cost. The exposure position is accurately determined by the wafer stage.

• Reliability and uptime. All handling systems and the stage are state-of-the-art, proven and therefore high reliability modules resulting in high uptime.

  Software is well known source of reliability issues. We use model driven software design methodologies to significantly improve SW reliability also for upgrades in the field. The system comes with a proven industry standard user interface providing Ease-of-Use, fast upgradability and robustness.

The most important capability of a lithography tool is to reproduce features as defined on the reticle as good as possible anywhere in the exposure field and anywhere on the wafer. The tolerable difference between the reticle feature and the printed feature on the wafer, referred to as CD Uniformity is usually 10% max. Fig. 2a and 2b show the CD Uniformity for 2 μm lines/spaces across the entire wafer for the LITEQ 500. Horizontal lines are printed with a 74 nm uniformity and vertical lines with a 59 nm uniformity (both 3σ), which is better than 3.7% of the target linewidth. In Fig. 3a and 3b the CD Uniformity has been split in a 60 nm (3.0%) variation across the exposure field (IntraField CD Uniformity) and a 21 nm (1.1%) variation between the different fields across the wafer (InterField CD Uniformity). The IntraField variations account for the aberrations of the optical system and the unflatness of wafer and waferchuck across the exposure field. The InterField variations account for the global flatness of the wafer and waferchuck and the repeatability of the autofocus and the dose control systems. Note that in order to show tool performance, a thin photoresist needs to be used. We used in our measurements 1.5 μm thick AZ MiR 703 resist from Merck. Any remaining resist process contribution mainly shows up in the Inter-Field CD Uniformity (the so-called process fingerprint). Estimation and subtraction of the process fingerprint in Fig. 3b would reduce the Inter-Field CD Uniformity from 1.1% to 0.9%.

The variations shown in Fig. 3 do not include contributions typically related to customer product wafers like e.g. wafer warpage, product wafer topology and thick resist processing fingerprints. The contributions from the Litho tool and the customer product wafers are statistically independent, although we have little information on their distributions. Therefore, the following equation approximately holds:

Given a tolerable max 10% total CD Uniformity (σ_total) and a 3.7% contribution from the Lithography tool (σ_tool), the tolerable contribution related to customer product wafers is still 9.3%. Therefore, with a 3.7% contribution from the lithography tool most of the tolerable error budget is available for variations typically related to customer product wafers.

A common way to express the available variation space for customer product wafers is the Usable Depth of Focus (UDoF), where the word ‘Usable’ refers to the fact that any focus variations related to the Lithography stepper, like e.g. Focal Plane Deviations of the lens, have already been excluded. On the basis of the above measurements the UDoF is over 15 μm.

This paragraph shows results for a range of resists and dielectrics used in Advanced Packaging. Both positive and negative tone materials are included.

The SEM X-sections in Fig. 4 show the LITEQ 500 resolution capability for a chemically amplified positive tone customer RDL resist. Although the system is qualified @ 2 μm L/S this figure shows that a significantly tighter resolution is attainable. The Depth of Focus of more than 27 μm has been measured in the middle of the exposure field.

Fig. 5 shows imaging results for thick resist that can be used for wafer bumping and copper pillars. This demonstrates performance on thicker, traditional materials as well.

Fig. 6 to 8 show results of the PMER^TM P-C* chemically amplified resist series, which has been designed for plating applications ranging from RDL to bumps, copper pillars and gold bumps. These versions show common characteristics like steep sidewalls and high speed. Both of these characteristics are emphasized in the LITEQ 500 system with its single wavelength of 355nm.

PBO is a dielectric, used for isolation layers and stress buffers. Since these materials become a permanent part of the device also electrical and thermomechanical properties are important. Fig. 9 shows the LITEQ 500 performance on a 15 μm thick film (before development). The ‘bowl-type’ shape is characteristic for this material, it provides a good metal conformity for the following plating step.

Polyimide is a different type of dielectric. Fig 10a and b show the performance of dense 10 and 15 μm VIA's in a 10.7 μm thick film before cure.

The Throughput of the LITEQ 500 system is amongst the highest in the industry because of the following reasons:

• Fast wafer handling and stage enabled by state-of-theart mechatronics technology

• Optimum size and shape of the exposure field. A very large field has a very good field filling efficiency for common die sizes, however the wafer filling efficiency in that case is very poor; there are relatively many edge fields with a lot of light loss. For a very small field it is the other way around. The LITEQ 500 field has the optimum field size and shape to maximize both the field and wafer filling efficiency

• The laser light source provides high intensity and does not show the decay over time as is the case in mercury lamp based systems

• Reticle masking (REMA) provides a fast and flexible way to support exposing multiple patterns, like e.g. for including fiducial marks to align wafers on other equipment in the Advanced Packaging process flow

Currently available Lithography systems that don't have REMA use multiple fields on the reticle, which has disadvantages:

• Multiple fields on the reticle require to move and realign the reticle when shifting to different reticle fields

• Depending on the implementation on the currently available systems it could also mean that the size of each of the multiple reticle fields needs to be reduced, simple because of space limitations. This will drive up the number of fields to be exposed, which will drive down the throughput

For practical multi-pattern use cases, the LITEQ 500 Cost of Ownership can be reduced by up to a factor of 2. This COO reduction is the combined effect of:

• The LITEQ 500 raw throughput, which is amongst the highest in the industry

• The use of fast and flexible reticle masking for multi-pattern use cases

• The cost effectiveness of the LITEQ 500 system amongst others enabled by the laser light source

Below a multi-pattern use case is presented with 2 fiducial marks on specific locations on the wafer in which the REMA is used to expose the different patterns. Fig. 11 shows the wafer layout and the relevant data. To show the effectiveness of the REMA the use case compares throughput with and without fiducial marks and wafer-ID clear-out.

This use case is implemented in the following manner:

• A small portion of the exposure field is used for the fiducial mark pattern as well as some patterns with fill-up die, which are needed to fill the area around the fiducial marks

• The remaining part of the reticle field is used as the main field to expose the product die on the wafer

• The wafer-ID clear-out is created by arranging the fields around that area

Fig. 12 gives the optimum reticle field layout for this use case and Fig. 13 shows the resulting wafer layout.

When using REMA the wafer exposure cycle looks like:

• Select the main field with the REMA, which is shown in Fig. 14

• Expose all main fields. The different colours of the fields in Fig. 13 are only to show the layout of the fields

• Re-blade the REMA to the block with 6 fill-up die, which takes a short time because of the high speed of the REMA, this is shown in Fig. 15

• Expose the 4 blocks with 6 fill-up die

• Repeat this cycle of REMA re-blading and exposure for the fill-up blocks with 2 and 1 die and for the embedded mark in a die

Running multi-pattern jobs has an impact on throughput. Systems using multiple reticle fields suffer from the time it takes to move and re-align the reticle when shifting to the next reticle field. The REMA operation is much more efficient, however, it also creates some overhead time

In order to make a throughput comparison the multi-pattern use case is compared to a use case with full wafer coverage of the 4×4 mm product die only. Fig. 16 shows this comparison for the REMA based LITEQ 500 system together with a representative system using multiple reticle fields. The figure shows that the combined effect of lower impact of the multi-pattern use case and higher raw throughput creates a significant advantage for the LITEQ 500 system.

A novel Lithography system dedicated for Advanced Packaging applications has been described. One of the new elements in the LITEQ 500 system is the use of a 355 nm laser light source, which creates advantages for imaging, throughput and Cost of Ownership.

This paper demonstrates imaging results for a range of resists and dielectrics, including both traditional materials as well as new chemically amplified materials.

The paper also demonstrates a multi-pattern use case showing the flexibility and throughput potential of reticle masking (REMA).