Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Moore's law [1] has been driving the system-on-chip (SoC) platform. Especially in the past 10+ years, SoCs have been very popular for smartphones, tablets, and the like. SoCs integrate different-function ICs into a single chip for a system or subsystem. Two typical SoC examples are shown in Figure 1. The application processor (AP) A10 is designed by Apple and manufactured by TSMC using its 16nm process technology. It consists of a 6-core graphics processor unit (GPU), two dual-core central processing unit (CPUs), 2 blocks of static random access memories (SRAMs), etc. The chip area is 125mm² and has 3.3 billion transistors. The application processor A11 is also designed by Apple and manufactured using TSMC's 10nm process technology. The A11 consists of more functions, including a tri-core Apple designed GPU, a neural engine for face ID (identity), etc. However, because of the Moore's law, i.e., the feature size is from 16nm down to 10nm, the chip area is about 30% smaller than that of the A10 and there are 4.3 billion transistors.

Why is heterogeneous integration of such great interest [2–14]? One of the key reasons is because the end of Moore's law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make SoCs. Some of the early researches in heterogeneous integration have been provided by Georgia Institute of Technology [2, 3, 4] where they reported a differential Si CMOS (complementary metal-oxide semiconductor) receiver IC (operating at 1 Gbps) integrated with a large-area thin film InGaAs/InP I-MSM (metal-semiconductor-metal) photodetector (Figure 2).

Heterogeneous integration contrasts with SoCs in the following manner. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions from different foundries, wafer sizes, and feature sizes (as schematically shown in Figure 3) into a system or subsystem, rather than integrating most of the functions at the chip level, using finer feature sizes. For the next few years, we will see higher levels of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption, signal integrity, or cost. Heterogeneous integration is going to take some of the market share away from SoCs for high-end applications such as high-end smartphones, tablets, wearables, networkings, telecommunications, and computing devices. System-in-package (SiP) [15]–[25] is similar to heterogeneous integration except less dense, larger pitch, and simpler. How should these dissimilar chips talk to each other? The answer is: redistribution layers (RDLs) [26, 27]! How should those RDLs be made? It can be made by FOW/PLP methods [28–33]. In this study, we use FOPLP technology.

In this paper, the feasibility of a chip-first and die facedown FOPLP of a heterogeneous integration of four chips is demonstrated. In order to have a very high-throughput and low-profile package and save the EMC, a process called Uni-SIP (uni-substrate-integrated-package) [11] is used to fabricate the RDLs. Unlike in [11], the panel dimensions in this study are 508mm × 508mm and a dry-film EMC is laminated on the reconstituted panel (instead of the liquid EMC with compression molding as in [11]).

The Uni-SIP process starts off by attaching the backside of the ECM-panel on both side of a coreless panel substrate with an epoxy resins material. (In this study, the chips embedded in the dry-film EMC is called ECM-panel.) The RDLs are formed on both surfaces of the ECM-panels. The ABF is used as the dielectric of the RDLs and is built up by SAP. The electroless Cu is used to make the seed layer, the LDI is used for opening the photoresist, and the PCB Cu plating is used for making the conductor wiring of the RDLs. The solder mask is then applied on both sides of the ECM-panel and leaving pad openings for surface finishing. The ECM-panels with build-up RDLs are finally separated from the coreless panel substrate mechanically. It is followed by solder ball mounting and dicing. This process adds a new dimension in high-throughput and thin fan-out packaging.

Figures 4 and 5 show the test chips (5mm × 5mm and 3mm × 3mm) under consideration. The layout of the test chip is shown in Figure 4, and the fabricated chips are shown in Figure 5. It can be seen that, for the 5mm × 5mm × 150μm chip, there are 88 pads with a pitch = 180μm (the outer rows). The polyimide opening of the Al-pad is 40μm in diameter and is 5μm thick. The SiO₂ passivation opening of the Al-pad is 110μm × 110μm, and the size of the Al-pad is 130μm × 130μm. The Cu contact-pad is 110μm in diameter and is 8μm tall from the Al-pad. The dimensions of the small chip are 3mm × 3mm × 150μm as shown in Figure 5. It can be seen that there are 48 pads on a 180-μm pitch (outer rows). The cross section and dimensions of the pads of the small chip are the same as those of the large chip.

Figure 6 schematically shows the test package under consideration. The dimensions of the test package are 10 mm × 10mm, and it consists of one large chip (5mm × 5mm) and three small chips (3mm × 3mm). The spacing (gap) between the large chip and the small chip is 100μm. These packages are to be made from a 508mm × 508mm reconstituted panel as shown in Figure 7.

Figure 8 schematically shows the cross-sectional view of the test package. It can be seen that there are two RDLs, and the thickness of the metal of RDL1 and RDL2 is 10μm. The linewidth and spacing of the metal of RDL1 are 20μm, and those of RDL2 are 25μm, respectively. The dielectric layer thickness of DL1, DL2, and DL3 is 20μm. The via through the first dielectric layer (DL1), connecting the Cu contact-pad of the test chip to the first RDL (RDL1) is 50μm in diameter. The pad diameter on the RDL1 is 135μm, which is connected to RDL2 through the via with a diameter of 50μm. Similarly, the pad diameter on the RDL2 is 135μm. Finally, 230-μm solder-ball Cu pads are formed on RDL2. The opening of the solder mask (DL3) is 180μm. The solder ball size is 200μm, and the ball pitch is 0.4 mm.

Figure 9 shows schematically the FOPLP with chip-first and die face-down assembly process. Basically, works must be done on the device (test chip) wafer [Figure 9 (left)] and the reconstituted panel [Figures 9(a) - (f)].

As shown in Figure 4 and the left-hand side of Figure 9, the original device (test) wafer must be modified with a Cu-pad on top of the Al-pad. Then, dice the wafer into individual known-good dies (KGDs) or test chips.

On the 508mm×508mm reconstituted panel (in this case, it is a piece of organic carrier), first attach a 2-side thermal release tape, Figure 9(a). Then, pick and place the test chips (face-down) on the tape, Figure 9(b). It is followed by laminating a dry film EMC (180°C for 60 minutes) on top of the reconstituted panel as shown in Figure 9(c). The material properties of the dry-film EMC is shown in Table I and is about 140μm above the back-side of the chips. Then, remove (debond) the carrier, we have the ECM-panel as shown in Figure 9(d). It is followed by stacking the backside of two ECM-panels on a core substrate with an epoxy resin on its both sides and by the standard PCB lamination process (180°C for 30 minutes), the Uni-SIP structure, Figure 9(e), is obtained. It is followed by peeling off the tape, Figure 9(f), the Uni-SIP as shown in Figure 10 is ready for fabricating the RDLs from the Cu-pads on its both sides.

The de-taping is very successful and there is no evidence of EMC cracking. The warpage of the de-taped double-side ECM-panel (Uni-SIP) is 0.918mm as shown in Figure 11.

Figure 12 shows the process steps in fabricating the RDLs for the Uni-SIP structure from the Cu-pads on both side of the structure. First laminate an ABF on both side of the structure. Then laser drills the ABF and stop at the Cu-pad (this is the reason for making the Cu-pad on the device wafer). It is followed by electroless Cu seed-layer plating. Then, laminate a photoresist dry film. It is followed by LDI and dry film development. Then, PCB Cu plating, dry film striping, and Cu seed layer etching. RDL1 is obtained (Figure 13).

Repeat all the processes to get RDL2 (Figure 14). It is followed by laminating a solder mask and making the SRO (solder resist opening), Figure 15. Then, mechanical debond the ECM-panels from the core substrate.

Figure 16(a) shows the x-ray image of the individual heterogeneous integration package of 4 chips and RDLs. Figure 16(b) shows the C-mode SAM (scanning acoustic microscope) image of the individual SiP of 4 chips and dry-film EMC. It can be seen that: (1) the chips are properly placed and molded, and (2) there is no void in the dry film EMC and between the gap (100μm) of the chips.

There are two different stencils for the solder ball mounting: one is for stencil printing the flux, and the other is for stencil mounting the solder balls. The solder (Sn3wt%Ag0.5wt%Cu) balls (200μm-diameter) used are from Indium. The peak temperature for solder reflow is 245 °C. Figure 17 shows the bottom-side of the individual SiP. It can be seen that there are 405 solder balls.

Figure 18 shows the cross sections of the heterogeneous integration of 4 chips. It can be seen that: (1) there are two RDLs, and (2) the chips, RDLs, and solder balls are properly assembled.

Some important results and recommendations are summarized in the following.

• ➢ A very low-profile (~390μm) heterogeneous integration of 4 chips by a FOPLP method has been successfully designed and fabricated.

• ➢ A very low-cost dry-film EMC has been successfully laminating on the 508mm × 508mm reconstituted panel with 1512 SiPs.

• ➢ There is not void in the dry-film EMC and the gap (100μm) between chips.

• ➢ A very high-throughput Uni-SIP process for fabricatingthe RDLs has been demonstrated.

• ➢ The de-taping of the ECM-panel didn't cause any EMC cracking.

• ➢ The maximum warpage of the double-sided ECM-panel(Uni-SIP structure) is 0.918mm, which is less than theallowable (1mm).

• ➢ Thermal cycling and drop tests should be applied to thetest samples to verify their reliability. These will be thenext tasks of this project.

The authors would like to thank the kindness of 3M, Nagase, Hitachi, Indium, and Disco for providing them with useful help and materials for this project. The constructive contributions from TJ Tseng, CM Lai, Casper Tsai, YM Chan, Leslie Chang, Eric Ng, TW Lam, JW Dong, and Jiang Leon are greatly appreciated.