fcLGA Package Assembly Qualification for Mobile Applications

Flip chip interconnects are in demand for consumer electronics as these packages shorten the signals, reduce inductance and improve functionality of these packages as compared to the wire bonded packages. These packages are commonly known as LGA (Land Grid Array) packages. To ensure reliability of these packages in high volume SMT assembly production requires careful selection of substrate materials, fluxes, component plating finishes, controlled reflow processes and warpage characteristics of package and substrate. [2]

This challenge is enhanced with the transition to lead free reflow as the higher peak reflow temperatures results in thermal and CTE mismatch between package and substrate. Proper storage and handling controls of components and process controls in production are necessary for good yields and reliability.

The paper summarizes the qualification of fcLGA solder interconnects on an organic substrate. Package construction analysis was conducted to assess integrity of the die attach, molding and plating processes.

The typical dies used for flip chip application are solder bumped silicon die manufactured using foundry processes. A film of passivation material is applied over the wafer circuit surface. This film provides mechanical stress relief for the ball attachment and electrical isolation at the die surface. Openings are created in the passivation film, providing electrical contact to the IC bond pad. A UBM-(under bump metallurgy) is added over the openings and the solder bump is paste printed and reflowed or electroplated and reflowed. Ball drop processes are also used for solder bumping the wafer. After electrical test, the wafer is singulated and the dies are packaged in Tape and Reel or assembled from wafer on film frame. The bump solder alloy typically used is SAC 305(Sn 96.5/3.0 Ag/0.5Cu). Flip chip dies typically have bump pitch of 200–250um and bump height of 70 to 85 um, however, dies designed as WLCSP (Wafer Level Chip Scale package) for direct surface mount reflow have wider pitch of 0.350 mm or higher and bump standoff height of 0.150 mm or higher and bump diameter of 200um or above. Figure 1 shows the X-Ray of a bumped die in package

Substrate used for the fcLGA assembly is typically a 2–4 layer thin organic laminate approximately 150–300 um thick. The material selection of the substrate is critical for successful reflow and bump integrity post reflow. The higher temperature lead free reflow requires laminates with high glass transition temperature (Tg) and low coefficient of thermal expansion (CTE) to minimize warpage during reflow. Typical substrates used are Bismaleimide Triazine (BT) Resin laminates with Tg ranging from 180–200C and CTE ranging from 14–15 ppm/C in XY and 55–60 ppm/C in Z direction.

Substrate survival thru multiple reflows and less than 10% delamination in critical areas after MSL pre-conditioning is an important criteria to consider for flip chip assembly qualification. The package for qualification is a 4×4×0.85 mm 32L fcLGA.

ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold) and. ENIG (Electroless Nickel/Immersion Gold) are the typical surface finish used on the copper traces and solderable pads. Organic Solderability Preservative coating over copper land pads if used for cost tradeoffs or other reasons should be carefully evaluated for bump reliability post reflow prior to manufacturing release. In general, Non Solder Mask Defined (NSMD) pads are preferred over Solder Mask Defined (SMD) pads for solder bump grid array packages, however, selection of NSMD vs SMD should be based on complexity of the board design and board suppliers' capability for solder mask registration and tolerance. Solder mask is recommended between all pads. The NSMD pads are illustrated in Figure 2 and the SMD pads are illustrated in Figure 3

The solder mask defined pads have mask encroaching on the substrate pad

Flip chip dies are typically picked up by vacuum nozzles from pocketed carrier tape reels and placed on to PCB substrates. Automated placement equipment with vision alignment is used for placement. Proper nozzle design is critical for damage free picking from Tape and Reel. Die placement pressure should be characterized and actual placement forces should be measured periodically using a calibrated load cell with meter.

The placement accuracy of the automated Pick and Place system is also dependent on its vision alignment of package outline centering vs bump grid array centering. Package outline centering is employed for higher speed placement with reduced alignment accuracy requirements and bump grid array vision centering is employed for maximum alignment accuracy at lower placement rate 2D transmission X-Ray inspection is required for placement accuracy verification and measurement [2].

The die placement step involves application of flux to the solder bumps either using a spray fluxing arrangement for the substrate or a flux dip station on the pick and place machine. Careful selection of the low residue flux with adequate tackiness is essential for proper coverage of the bump with flux. Flux dip should involve wetting of at least 1/3 of the total bump height with flux. An alternative method uses solder paste print or dip process. This provides added solder volume and provides a higher standoff height post reflow and facilitates flow of cleaning fluids under the solder bumps. In either case, proper calibration of the solder/flux volume is essential to ensure that consistent volume of solder or flux is delivered on all units on the substrate strip.

The assembly flow was determined based on several experiments conducted to define and optimize process for placement and reflow.

The typical flip chip assembly process flow is as shown in Figure 4.with under fill as an optional process. For the fcLGA qualification, the solder paste print process was used.

The reflow profile is a critical part of the flip chip assembly process. A proper reflow profile must provide adequate time for flux activation and volatilization, proper peak temperature, time above liquidus, ramp up and cool down rates. The profile used has direct bearing on manufacturing yields, solder joint integrity and the reliability of the assembly. During mass soldering, it is important that all solder joints reach the minimum soldering (reflow) temperature to assure metallurgical bonding of the solder alloy and the base metals to be soldered. Metallurgical bonding requires that both surfaces to be soldered, as well as the solder, reach this minimum soldering temperature for a sufficient time to allow the wetting of the solder surfaces per IPC -7530 -Guidelines for Temperature Profiling for Mass Soldering (Reflow & Wave) Processes [3]

Figure 5 shows the lead free flip chip reflow profile.

The package when subjected to the reflow process does experience some warpage due to the thermal strain mismatch among the materials used to construct the package. It is important to conduct warpage characterization during the reflow soldering cycle as package warpage can result in open or short circuit connections. There are many measurement tools that are used to measure package warpage as shown in JEDEC – JESD22-B112A-Package Warpage Measurement of Surface Mount Integrated Circuits at Elevated Temperature [4]

Visual and 2D X-Ray inspection is recommended after solder reflow for solder joint size and shape irregularities. Well reflowed solder joints show evidence of good wetting of copper pads with uniform solder surface appearance. Flip chip solder joints should be inspected for uniform ball collapse after reflow. Visual inspection and X-Ray can also support inspection of solder shorts, insufficient solder, voids within solder joint and potential solder opens. Sample tilt capability in X-Ray may be required to look for solder opens. X-sectioning Solder joints assists in verifying visual defects. Solder joint acceptance criteria defined in IPC-610 should be used for inspection. [5]

The package is over molded using epoxy based mold compounds to protect the reflowed die from any environmental, handling and foreign material damage. Under fill application was not used as the pin count is low and package is not large size (4×4 mm). MUF (Molded under fill) is applied where mold compound acts an under fill and over mold.

X-sectional analysis of the package is conducted to understand the internal structure of the package. Any assembly abnormalities seen here are highlighted to the assembly team and optimized prior to production start. Figure 6 shows the bottom side of the assembled package showing the terminations and the center pad layout.

The X-sectional analysis evaluates several items, including the uniform bump collapse, corner vs center joints, mold cap height, total package thickness, solder voids, substrate thickness etc. as shown in figure 7 and figure 8.

Figure 8 shows more package details in a magnified image.

The solder voids were evaluated in the X-sections. Some voids were observed, however they were below the 25% spec allowed per IPC-610. [5] Proper optimization of the reflow profile helps minimize this condition. Figure 9 shows bump voids.

The X-sectional analysis also helps evaluate the substrate copper and Prepreg layers and the vias. Figure 10 shows the PCB layers and the vias.

The qualitative assessment and the measurements conducted in the X-sectional analysis help characterize the package and ensure that it meets the package outline drawing. Any optimization needed in the assembly process is conducted prior to release to the manufacturing process.

The assembly qualification testing is conducted per JESD47–Stress Test Driven Qualification of Integrated Circuits. [6] The assembly qualification is conducted using three qualification lots of 1000 unit minimum. The assembly yield of each lot is monitored. Table 1 shows the assembly Yields.

Table 2 shows the process workmanship data post reflow. Die peel test is conducted to check for wetting of the bump post reflow. X-ray is conducted to ensure proper alignment of the die on substrate pads.

Five samples are analyzed per lot to assess workmanship.

Solderability test was conducted per J-STD-002D [7] to ensure that each solderable termination was at least wetted 95% as shown in Figure 11

Delamination check was conducted after MSL-3 pre conditioning at 30C/60% RH for 192 hours followed by 3X reflow at 260C. CSAM was conducted using scanning acoustic microscopy. The samples met the acceptance criteria of less than 10% delamination in critical areas per JEDEC spec J-STD -020E [8]. Figure 12 shows the pre and post CSAM images of the samples.

Reliability testing is conducted on samples from 3 lots per JEDEC requirements. Thermal cycling, high temperature storage and HAST (Highly Accelerated Stress test) were conducted. All samples passed the final electrical read points. Table 3 summarizes the test conditions and results

Flip chip assembly for fcLGA can be successfully qualified with the proper characterization of the package assembly process. Successful qualification requires understanding of the industry standards, customer requirements and partnerships with knowledgeable and experienced subcontractors. Early engineering interface and proactive preparation of process controls based on the learning during process development and qualification facilitates in a smooth product launch.

The author wishes to acknowledge the Failure Analysis and Reliability labs and the Quality and Test teams for assisting with inspection, qualification and testing of this package.