Design and demonstration of Glass Panel Embedding for 3D System Packages for heterogeneous integration applications

This paper demonstrates an advanced 3D Glass Panel Embedded (GPE) packages for heterogeneous integration of digital applications requiring high-density interconnections and RF applications with Through-Glass-Vias (TGVs) integrated in the fan-out region. Using advanced process technologies to overcome the limitations of current Wafer Level Fan-Out (WLFO) packages, this paper demonstrates a 3D fan-out package capable of handling Si-like RDL along with superior electrical performance and reliability of glass, not possible in other organic fan-out solutions.

The demand for computationally intensive applications and the drive to move the computational horsepower to the server side is driving a critical need for next generation of high-performance computing architectures with very-high density RDL and support for BEOL-like I/O pitches. Today, the most widely used architecture for such an application is the 2.5D Silicon Interposer which becomes very expensive as the package sizes increase. Recently, Embedded Si-Interconnect Bridge and RDL-first approaches have been demonstrated as cost-effective methods of scaling to larger packages [1,2]. However, these architectures, just like silicon interposers, are bump limited and are hence prone to slow-throughput assemblies. WLFO packages, on the other hand, have disrupted the entire semiconductor industry in their ability to scale to very fine I/O pitches enabling unparalleled power and signal performance. Although it was initially designed to extend package I/O counts beyond fan-in Wafer Level Packages, the scope of WLFO technology has expanded significantly in recent years to include multi-die SiP modules with high-density RDL, as well as high I/O logic and memory integration. Most WLFO packaging technologies today use epoxy-based mold compounds [3,4]. However, such WLFO packages are fundamentally limited in scaling up to high-density, high-I/O applications because: (i) mold compounds have a huge CTE mismatch with silicon affecting reliability (ii) It is difficult to populate high-density fine RDL on mold compounds (iii) mold compounds suffer from large area warpage that hinder panel-scale processing. Due to these reasons, it is difficult to use current WLFO technology for large packages (>40×40mm) in high-bandwidth computing. Most importantly, current WLFO packages are also prone to severe die-shifts that arise from the mold filling and shrinkage during processing [5]. Although, many studies have been conducted to predict and compensate for die-shift and control surface planarity, they continue to be an important factor limiting the potential of WLFO packages.

In [6], Georgia Tech presented the first demonstration of glass panel embedding. Glass, when used as a carrier for die embedding, not only outperforms other organic solutions, but also provides many other benefits not found in existing WLFO technologies. In [7], improvements to the GPE process was demonstrated to include multi-die embedding within a single cavity. The smooth surface and high-dimensional stability of glass enables high-density silicon-like RDL wiring and BEOL-like I/Os even on large panels, thus increasing productivity and lowering cost, bringing an unparalleled combination of high I/Os and low cost not possible in mold compound-based fan-out. The CTE of glass can be tailored, thus, improving reliability and enabling the direct surface mounting onto the board unlike some high-density fan-out packages that require an organic package to connect to the board for large body sizes. Glass has ~2–3× lower loss-tangent as compared to mold compound, making GPE an ideal candidate for high-speed and high-frequency applications. Glass also provides high resistivity, excellent moisture resistance and high surface smoothness as compared to mold compounds. Although glass based embedded fan-out packages promise superior benefits, there is a continuing need to improve I/O density, electrical & thermal performance, yield, cost and chip- & board-level reliability of GPE packages. High-yield, Low-cost panel- scale processing of embedded GPE packages are primarily limited by die shift, panel warpage, non-coplanarity issues and lack of production tools.

By addressing the critical parameters of die drift and surface planarity, this paper presents the first demonstration of a 3D Glass Panel Embedded (GPE) package for large body size integration with better performance, cost, and reliability than existing technologies. This paper is organized as follows: Section 2 describes the process flow in fabrication of these 3D embedded packages and section 3 lays out the results and presents a discussion. Section 4, in conclusion, summarizes some of the key process advances described in the paper and lists some of the future work.

Based on the formation of glass cavities, 2 different architectures were considered to realize a 3D GPE package: 1) Blind-cavity GPE and 2) Laminated-Cavity GPE [7]. In blind-cavity GPEs, the cavities are, basically like wells, formed on bare glass by wet-etching methods. Based on the thickness of the dies, the cavity depths are controlled by optimizing the etching process. The vias are then drilled with respect to the position of the cavities on the panel. This paper demonstrates a process technology for 3D integration in blind-cavity GPE, the process flow of which is shown in Figure 1 and each of the steps are detailed in this section.

To emulate embedded devices, daisy chain test dies, with a mean size of 7.2 mm × 7.2 mm and mean thickness of 100 μm, provided by Global Foundries were used (shown in Figure 3(a)). The dies are un-bumped with a pad pitch of 50 μm in one direction and 40 μm on the other. Based on this, the blind-cavities were designed at 7.5 mm × 7.5 mm and 200 μm glass panels were structured by AGC with cavities of 110 μm as shown in Figure 2(b). At first, the Through-Glass-Vias (TGVs) were drilled along with corner alignments markers, following which blind cavities of 110 μm depth were wet etched. The positions of these cavities on the panel was set using the alignment vias on the panel ensuring all the TGVs are aligned to their respective cavities.

The blind-cavity glass panels were then patterned on the back side to aid alignment of dies when placing them in cavities. These back-side alignment guides provide panel scale die to TGV alignment and are also used to align the subsequent RDL layers. Two approaches in die-embedding were studied to ensure the die-shift was minimized. The results from these studies are discussed in the next section. In the first approach, after the two glass panels are laminated using the polymer adhesive, the dies are embedded in the cavities using a precision placement tool from Finetech and then the polymer is cured to flow around and the die harden in the process. In the second approach (shown in the process flow Figure 1), the dies are first laminated on to a 10 μm Die Attach Film (DAF) from Nitto Denko following which they were singulated and placed in the glass cavities (shown in Figure 5). The DAF was then cured using an optimized cure profile to minimize die shift during the cure. Figure 6 shows the microscopic image of die-to-die alignments.

RDL polymers from Ajinomoto (ABF GY11) were then laminated and cured on both sides to minimize the warpage of the ultra-thin package. The smaller filler particles in ABF GY11 make it transparent which enables the measurement of die drift even after the polymer is cured. Two layers of 15 μm ABF GY11 is used on each side so as to accommodate for the polymer flowing into the cavities. The lamination and curing conditions of ABF GY11 is optimized to maximize the flow during the cure so that they fill up the cavities and the TGVs completely. Figure 7 shows the glass panels after the lamination and cure of ABF GY11.

A surface planar tool by Disco was then used to planarize the surface of the panel to avoid non-coplanarities that may arise from the polymer filling up the cavities. This step is important for high-density applications that require a highly planar surface to populate fine RDL. A picosecond UV laser tool from ESI is used to drill blind microvias to expose the bumps on the die. A drill test was conducted with varying power and repetitions to optimize the aspect ratio of the via. Figure 8 shows the 3D image of the drill test and also the microscopic images of the vias drilled on the dies to expose the pads. The drills were controlled to ensure an opening of 22 μm and a bottom of 10 μm. The excellent alignment accuracy of the vias comes from the superior dimensional stability of glass that cannot be found in other organic substrates. Such alignment accuracies are critical in panel scale embedding of dies with fine pitch large I/O counts. After this, the US laser was used to drill vias inside of the polymer-filled TGVs, thus establishing a via-in-via scheme. Such a scheme mitigates the yield issues that may arise from TGV defects and improves plating reliability. Figure 9 shows the drilling process of such via-in-via structures.

Redistribution layers are formed using standard semi-additive processes (SAP). Electro-less deposition of Copper is used to form a seed layer of 300 nm. This process also metalizes the walls of the vias in a conformal manner. This is followed by photolithography of RDL layers and then 4–5 μm of Cu is deposited through electrolytic plating. The photoresist is then stripped off before the copper seed layer is differentially etched to form the RDL lines. Figure 10 shows the cross section of the 3D embedded glass package. Figure 11 and 12 show the cross-sections after double-sided RDL plating to form the chip-package blind via interconnect and through-package-via connection respectively. Such an architecture achieves the ultra-short interconnects by getting rid of an interposer/BGA Package which adds parasitics at every assembly level. These packages can now be directly mounted on the board after screen-printing of BGAs. Direct-board mounting achieves excellent miniaturization while ensuring superior electrical performance.

In order to achieve high-density integration in embedded packages, it is critical to study the die shift during the entire processing of the panel. Dies embedded drift when the polymer under or around them shrinks during the cure. This results in a drop in the yield due to misalignments, and this drop is more pronounced as we scale to smaller I/O pitch and importantly in high-density multi-chip packages. The other important parameter in achieving the RDL would be the planarity of the dielectric surface post embedding. These two critical factors are studied in detail in this section.

As described previously, two different approaches in die-embedding are considered and studied to ensure the die shift is minimized [7]. In the first process, the die was placed on the polymer adhesive used to bond the two glass panels together and cured using two different cure profiles. Condition 1 uses a traditional temperature profile while Condition 2 uses a 2-step cure. The first step involves a lower temperature (where the polymer remains highly viscous) partial cure for a long duration before the second step which ramps to the traditional, higher cure temperatures. Optical characterization (shown in Figure 11) showed considerable reduction in the die-shift in condition 2 as compared to condition 1 (shown in Figure 13). In the second embedding approach, DAF to adhere the die to the cavity.

In order to improve the accuracy in measurement of die shift, a metrology scheme using ESI laser tool was developed. The panel was held by vacuum on the stage of the laser tool and the coordinates of the corners of the die and the panel were acquired as shown in Figure 12. This process is repeated after the curing steps and the die-shift was measured by using a trilateration algorithm. A comparison of die-shifts between each process measured after the embedding process and after the dielectric lamination process is shown in Figure 13. Such a metrology scheme is made possible by the excellent dimensional stability of glass that maintains near-zero registration anomalies during processing.

One of the primary challenges in moving to <5 um L/S RDL in embedded Fan-out packages include the non-coplanarities that arise from height differences between the dies and also between the substrate and the die. In order to achieve a flat surface while also filling the glass cavities with polymer completely, the lamination and cure conditions were optimized. Although, ultra-flat and smooth surfaces can be obtained through planarization, process improvements were needed to avoid dimples on the surface arising from the gap between the die and the glass panel.

The effect of lamination time, pressure, temperature and dielectric thickness on the surface planarity was evaluated. From Figure 14, it can be seen that, prior to these improvements, the dimple was ~ 40 um which would make it impossible to build RDL on top. With non-coplanarities of ~5um, it may even be possible to avoid fly-cutting in certain applications.

This paper demonstrated for the first time a radical new concept in next generation of 3D packages by glass panel embedding (GPE) with better I/O density, performance, cost and reliability than silicon interposers, embedded bridge and high-density fan-out packages for heterogeneous integration. A key enabler for the ultra-thin, panel-scale 3D GPE packages is the drastically reduced near-zero die shift during embedding and reliable TPVs and surface planarity, which were optimized by a systematic parametric process study. Precise cavities were formed in glass panels with low-cost and scalable processes. Cavity die-assembly processes were developed and optimized. Blind-vias and via-in-vias were drilled after the drill conditions were optimized to expose the Copper bumps pads on the die and open up the substrate for double side device assembly respectively. A new metrology scheme was developed to measure die-shift accurately and it was shown that the mean die-shift was <2 μm. The Surface Planarity was drastically improved to <5 μm before fly-cutting. This novel process presents a high-performance, robust and low-cost integration scheme to address future needs in heterogeneous integration.

The authors would like to acknowledge the tool, material and process support of ESI, K&S, Finetech, Ajinomoto and Dow Chemicals, Asahi Glass Company and Schott AG. The authors would also like to thank Chris White in assisting with the fabrication processes.