Abstract
The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of IC packages with conventional (small) stand-off heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: 1) attributes of the manufacturing process, 2) solder material properties and 3)design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the PCB-package assembly and particularly to the differences in the thermally induced curvatures of the PCB and the package. In this analysis the stress-and-warpage issue is addressed using an analytical predictive stress model. This model is a modification and an extension of the model developed back in 1980-s by the first author. It is assumed that it is the difference in the post-fabrication deflections of the PCB-package assembly that is the root cause of the solder materials failures and particularly and perhaps the HnP defects. The calculated data based on the developed analytical thermal stress model suggest that the replacement of the conventional ball-grid-array (BGA) designs with designs characterized by elevated stand-off heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design referred to as ball-grid-array (BGA) and a design with solder joints with elevated stand-off heights referred to as column-grid-array (CGA) are compared. The computed data indicated that the effective stress in the solder material is relieved by about 40% and the difference between the maximum deflections of the PCB and the package is reduced by about 60%, when the BGA design is replaced by a CGA system. Although no proof that the use of solder joints with elevated stand-off heights will lessen the package propensity to the HnP defects is provided, the authors think that there is a reason to believe that the application of solder joints with elevated stand-off heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.
I. Introduction
The causes of the observed head-in-pillow (HnP) soldering defects in Ball-Grid-Array (BGA) packages, and particularly those with lead-free solders [1–9], are attributed by many electronic materials specialists to process-related, solder-material-related and design-related issues. There is an indication that the design-related problems are caused by the elevated interfacial stresses and elevated warpage of the PCB-package assembly. A typical package structure is addressed in our analysis with an emphasis on the stresses and warpage issue. It is felt that it is the elevated interfacial thermal stresses and the difference in the post-fabrication thermally induced deflections of the warped PCB and the warped package that might be the root cause of the possible HnP defects, as well as of an insufficient interfacial strength of the solder joint interconnections.
The advantages of the elevated stand-off heights of solder joint interconnections, as far as the thermal stress level is concerned, have been first indicated in application to flip-chip solder joints about three decades ago [10,11] and has been recently addressed and modeled in application to the solder joints of the second level of interconnections [12], with an emphasis on the advantages of the column-grid-array (CGA) designs [13–18]. The analytical thermal stress model used in the analysis that follows is a modification and an extension of the previously developed constitutive thermal stress model [19].
II. Analysis
A. Interfacial Shearing Stress
The following simple formula was obtained for the interfacial thermally induced shearing stress acting in the solder joints of the second level of interconnections [19]:
Here Δt is the change in temperature from the soldering temperature (at which the thermal stress is considered to be zero), to the low (room, testing or operation) temperature (at which, at least when an elastic approach is used, the thermal stresses reach their maximum values), Δα = α1 – α2 is the CTE mismatch of the assembly's bonded components (the PCB and the package), α1 and α2 are the effective CTEs of the component materials (#1 is the PCB and #2 is the package) that should be assessed for the composite structures of the PCB and the package, h1 and h2 are the thicknesses of the PCB and the package, 
and 
are the axial compliances of the assembly components, E1 and E2 are the effective Young's moduli of the component materials, ν1 and ν2 are the effective Poisson's ratios of the composite structures in question, 
, 
and 
are the longitudinal interfacial compliances of the solder layer (including the underfill encapsulant, if any) and the composite structures of the assembly components, 
, 
and 
are shear moduli of the materials, λ = λ1 + λ2 is the total axial compliance of the assembly (note that the bonding layer, as long it is thin and low modulus, does not contribute to this compliance), 
is the parameter of the interfacial shearing stress, κ = κ0 + κ1 + κ2 is the total interfacial compliance of the assembly (the bonding layer plays here a significant role),
are the thermally induced forces acting in the cross-sections of the assembly components (tensile - in the PCB and compressive - in the package), and l is half the assembly length. The origin of the longitudinal coordinate x is in mid-cross-section of the package/PCB assembly.
B. Peeling Stress
The peeling stress (the interfacial normal stress acting in the through-thickness direction of the solder system) can be evaluated for a sufficiently long assembly with a relatively stiff interface (in the through-thickness direction) by the following formula [20]:
Here 
is the parameter of the peeling stress,
is the spring constant of the solder system (in the through-thickness direction),
is the parameter of the assembly thickness,
is the factor that characterizes the ratio of the parameters of the peeling and the shearing interfacial stresses,
is the peeling stress at the assembly ends,
is the parameter that characterizes the difference in the thicknesses and axial compliances of the assembly components. At the assembly ends (x = l), where the peeling stress reaches its maximum value,
If the assembly is very stiff in the through-thickness direction, i.e. characterized by large η values, then the formula (4) yields: p(l) = p0. This result explains the physical meaning of the p0 value.
C. Warpage
The thermally induced bow (warpage) of the assembly as a whole can be determined from the approximate equation of equilibrium of the elastic moment (left part of this equation, containing flexural rigidities of the assembly components) and the thermally induced “external” bending moment in the right part of this equation:
Here 
are the flexural rigidities of the assembly components (PCB and package) treated here as thin elongated plates. From (5) the following formula for the assembly curvature w″(x) can be obtained:
where
is the curvature in the middle of a long-and-stiff assembly. As evident from (6), the assembly curvature changes from its maximum value
in the middle of the assembly to zero at its ends. The angles of rotation of the assembly cross-sections can be found from (6) as follows:
Assuming that the assembly ends have zero deflection, this expression results in the following formula for the deflections:
In the middle of the assembly (x = 0)
In the case of a long and/or stiff assembly (large enough kl values),
For assemblies having very high k values of the parameter of the interfacial shearing stress (stiff PCB, stiff package, and stiff solder system) this formula yields:
III. Numerical Example
Input data
Coefficients of Thermal Expansion (CTE):
PCB α = 15x10–61/°C; Package α = 10x10–61/°C
Young's moduli:
PCB E =17900kg / mm 2;
Package E = 10300kg / mm 2;
Solder E = 5510kg / mm2;
Poisson's ratios:
PCB ν = 0.40; Package ν = 0.35; Solder ν = 0.35;
Shear moduli:
PCB G = 6393kg / mm2;
Package G = 3815kg / mm2;
Solder G = 2040.7kg / mm2;
Thicknesses (stand-off heights):
PCB h = 0.33mm; Package h = 0.33mm;
Solder/with regular stand-off height (labeled as “BGA”) h = 0.6mm;
Solder/with elevated stand-off height (labeled as “CGA”) h = 2.2mm;
Assembly size (half-length)
l = 20.0mm;
Change in temperature
Δt = 150°C.
Computed data:
Axial compliances of the assembly components:
Interfacial compliances of the assembly components:
Total interfacial compliance of the assembly:
Parameter of the interfacial shearing stress:
Product kl of the parameter of the interfacial shearing stress and half the assembly length
kl = 0.7175x20 = 14.350 for the BGA design, and kl = 0.4072x20 = 8.1440 for the CGA design.
In either case this product is significant, so that the assembly can be treated as a long one.
Thermal force in the mid-cross-sections of the assembly (stand-off height independent):
Highest interfacial shearing stress (at the assembly ends)
Axial compliance related parameters:
Doubled maximum interfacial peeling stress at the end of a long-and-stiff assembly
Interfacial through-thickness spring constant is
with the BGA solder system; and is
with the CGA solder system.
Parameter of the peeling stress
in the case of the BGA design and
in the case of the “CGA” design
Ratio of the parameters of the interfacial peeling and the shearing stresses
in the case of a BGA design
in the case of a CGA design.
Peeling stress at the assembly end
in the case of the BGA system
when the CGA system is employed.
Effective stress (based on the strength theory of the prevailing role of the shearing stresses)
in the case of a BGA
in the case of a CGA.
Flexural rigidities of the PCB and the package:
Curvature in the middle of a long-and-stiff assembly:
Maximum bow:
with the BGA design:
with the CGA design:
Difference in the maximum deflections of the PCB and the package
in the case of the BGA design and
in the case of the CGA design.
IV. CONCLUSION
The application of the elevated stand-off heights compared to the conventional solder joint system designs, can result in significant stress and warpage relief and, supposedly, in a high likelihood that the propensity of the IC packages to the observed HnP defects could be minimized as well. Future work should include both FEA and experimental investigations. Particularly, it should be verified if indeed packages with elevated stand-off heights of the solder system are less prone to the observed HnP effect related damages.
