Comparisons of Soldering Alloys in Large Ceramic Substrate to Metal Heatsink Attachment Application

Electronic components must be protected from corrosive, humid environments to ensure acceptable service life and reliability. In most of the cases, conformal coating is not enough. Most of the commercial power modules are encapsulated by polymer. Some of the high reliability power modules are hermetically sealed in a metal package protected by inert gases.

Most aerospace and military electronics need to meet the requirements of MIL-PRF-38534 and MIL-STD-883. MIL-PRF-38534 is a top level specification issued by the military logistics center, the Defense Logistics Agency (DLA). MIL-STD-883 is a military and aerospace electronic test standard to determine resistance to environmental elements and military and space operating conditions. The purposes of the MIL-PRF-38534 and MIL-STD-883 are to warrant the customers buying military level DC-DC converters at certain class levels come with a certain level of confidence with the United States government periodically checking on the electronics supplier's systems. The MIL-PRF-38534 and MIL-STD-883 specifications are to ensure that the electronics can withstand rigorous environmental stresses and are electrically stable with long-term use.

In aerospace electronics and especially in satellite power electronics applications, the environmental temperature as defined by MIL-PRF-38534 and MIL-STD-883 can swing between −65°C to +165°C. After 110 thermal cycles, the electronic device has to withstand 1500 g shock, 20 g (root mean square) vibration and 5000 g acceleration. With this type of large temperature swings, the material CTE mismatches are the dominating factors that define the reliability of space electronics.

Under large temperature swings, the hermetically sealed microcircuits, using multichip, multilayer thick film ceramic substrate technology, have great advantages over encapsulated electronics. The main reason is that the hermetically sealed microcircuits do not have encapsulant exerting large forces over components, solder joints and wires due to coefficient of thermal expansion (CTE) mismatches and glass transitions of the encapsulating polymers. These thermal mechanical forces are cyclical and cause solder joint and component fatigues.

Therefore, multichip, multilayer thick film ceramic substrate technology is still alive and kicking in aerospace electronics and particularly in space applications. The hermetically sealed multichip, multilayer thick film ceramic substrate technology is sometimes referred to as hybrid technology.

Even without stress-inducing polymer encapsulant, hybrid technology designs also have CTE mismatch challenges. Large ceramic substrate to metal heatsink attachment application is unique due to the large linear dimension and the CTE mismatches of the two different materials. The ceramic substrate is normally attached to a metal heatsink for structural support and for heat dissipation.

With the advancement of electronics, the substrate is getting larger in order to host more electronic components. CTE mismatches between the metal heatsink and ceramic substrates induce significant thermal mechanical stress to the attachment materials. The most popular ceramic to metal attachment material is solder.

The key requirements that drive the design are 168 hours, 125°C stabilization bake, per MIL-STD-883, method 1008; particle impact noise detection (PIND) per MIL-STD-883, method 2020; 110 temperature cycles, between −65°C to 150°C per MIL-STD-883, method 1010; 5000g constant acceleration per MIL-STD-883, method 2001; 1500g mechanical shock per MIL-STD-883, method 2002.

Under the above conditions, the stabilization bake causes growth of the intermetallic layer and phase coarsening which will weaken the solder. The thermal cycling causes the solder joints to fracture due to the ceramic substrate and metal heatsink CTE mismatches. Typically, the thermal cycling induces the latent defects in substrate to heatsink solder joints. The latent defects could turn to patent defects during the next few steps: PIND, constant acceleration and shock.

Initial finite element analysis (FEA) and test data indicate the traditional published bulk solder material properties do not match the tested material properties. The solder is much weaker than expected. Literature research, tests and FEA analyses were performed to study these two types of solders.

Despite recent restrictions related to lead content, some industries continue to use lead based alloys in solder applications. Multilayer thick film ceramic substrate technology in microcircuit electronics built for space applications uses both tin-lead-silver alloy Sn62 (Sn 62%, Pb 36%, Ag 2%) and lead free solder alloy Sn96 (Sn 96.5%, Ag 3.5%). Tin-lead based alloys, in particular, have proven to have excellent solderability to tin, nickel, copper, gold, and silver metallization surfaces. Tin-lead solders also performed better at resisting high cycle fatigues in normal operating temperatures than did most of the lead free solders. As a result of this, they are still widely used in aerospace and military electronics industry where high cycle fatigue is most likely the highest stress.

However, in one particular application, the lead free solder alloy Sn96 (Sn 96.5%, Ag 3.5%) behaves better than tin-lead solder. That is the ceramic substrate to metal heatsink attachment application. In this application, the low cycle thermal fatigue is the dominating stress factor.

Pb phase coarsening of eutectic Pb/Sn during stabilization bake is one of the reasons the Sn96 performs better. Lead free Sn96 solder is less sensitive to stabilization bake. High single element (Sn) contents reduce phase coarsening. Stabilization bake also causes intermetallic layers to grow. Gold embrittlement is a concern.

Sn96 has more tin (Sn) contents than Sn62. It can absorb more gold. The Sn62 eutectic also reduces the gold diffusion rate. Gold-tin intermetallic is more likely to concentrate in one area of the Sn62 and causes local embrittlement and fractures. That is why the Sn96 has better gold embrittlement resistance.

Since Sn96 has a higher melting temperature than Sn62, it has a lower operating temperature to melting temperature ratio. Sn96 has a higher ultimate tensile strength at higher operating temperatures than Sn62.

Literature studies per references listed below indicate that Sn96 should perform better than Sn62 in substrate to header attach applications. A set of tests are designed to verify the above mentioned literature research.

Although there is no static pull requirement, static pull test has a much better controlled environment than constant acceleration. The load can be recorded. Stress can be calculated. During constant acceleration testing, only failed or intact status can be recorded.

Solders normally do not fail under compression load. They fail under tensile and shear loads. From multiple previous tests and FEA analyses, the determining load in this application is the tensile load to the solder that causes the ultimate failure of the solder bond between the ceramic substrate and the gold plated metal heatsink. The test coupons as described below will be subject to 160 hours of stabilization bake at 125°C and 110 thermal cycles between −65°C to +165°C. Then the test coupons will be pulled with the Instron® electromechanical universal testing machine. By comparing the test results with the assist of the FEA software, the conclusions can be derived.

Test coupons are designed to simulate the real application while keeping all parameters in control. There are two types of pull test coupons used.

Both center pull and corner pull test coupons are designed to have lower stress at the substrate-to-heatsink interface and higher pull-tab-to-substrate interface. However, due to the larger diagonal dimension of the substrate to heatsink interface, the substrates were also observed separating from the heatsink.

Center pull test is designed to ensure the ceramic substrates are subject to a balanced load. The tensile loading is applied to the geometric center of the substrate and is designed to have balanced constraints around the center pull tab. The tab is designed to be at the center of the pull test fixture.

The corner pull test is designed to investigate the solder strength from a different mechanical angle. By applying a load to the center of the substrates, the load conditions are different. Therefore, the results from the center pull test will be further validated by shifting the load application inaccuracies

From previous test data, Sn96 and Sn62 solder behave similarly. The corner pull data and the center pull data correlated well.

Sn96 does not see degradation after 168 hour stabilization bake. Sn62 shows obvious degradation after 168 hour stabilization bake. Sn96 solder coupons do not demonstrate material strength changes. Sn96 has better overall strength than Sn62.

During the test, some test coupons had ceramic substrate to metal heatsink separations. All coupons with substrate to header separations used Sn62. Sn62 loses a great deal of strength during stabilization bake and thermal cycling.

Sn96 is estimated to be approximately two times stronger than Sn62 after stabilization bake and 110 thermal cycles. Theoretical material strength ratio is 3.23 times the published Sn96 tensile strength at break under static load which is 156 MPa. Sn62 tensile strength at break under static load is 48.3 MPa. Both center pull and corner pull coupons demonstrated around 50% reduction in solder strength.

Post-test FEA is to investigate the reason that some substrates fractured during center pull test as shown below.

FEA analysis indicated the ceramic substrate region immediately below the fillets had stress levels higher than the ultimate strength of the ceramic material.

The purpose of these tests is to validate the findings of the static pull tests. Since the requirement is constant acceleration, not static pull, constant acceleration tests need to be performed to ensure that different test methods will not alter the conclusion.

A number of different substrates are soldered to the heatsink and attached with simulated weight. The solders used are Sn96 and Sn62. All test samples experience the same level of thermal stress and acceleration loads. The results are as shown below.

The constant acceleration tests validated the findings of the static pull tests. The Sn62 solder is showing much larger degradation after stabilization bake and thermal cycling. Sn96 is showing higher resistance to thermal fatigue than Sn62 as demonstrated during static pull tests.

Static corner pull, center pull and constant acceleration tests are all pointing to similar results. The Sn96 is a more suitable solder for MIL-PRF-38534 applications than Sn62.

Solder material strength diminishes because of the following factors: void, intermetallic compound (IMC) formation, bond line thickness (BLT), actual reflow profile (preheat, peak, duration and cooling), contact surface roughness, plating (chemical differences, thickness, material crystallization), contaminants (both surfaces, solder, flux), flux (quantity, quality, wetness, activation, duration, flux removal), cooling rate (after exit from oven), geometric alignment (especially for smaller sized preform), solder alloys and the purity of the alloy.

After stabilization bake and thermal cycling, the Sn96 solder strength will further reduce to 50% of the original level. Sn62 will decrease to 25% of the original level. This strength reduction should be accounted for during the initial design phase. Since the overall solder material property can vary in such large scales, it is suggested to use twice the design margin to cover those variations for Sn96 solder.

New designs should be evaluated with FEA software by comparing with the existing design. The stress, strain, and strain energy density of the new design should not exceed the existing design. The maximum stress, strain, and strain energy density should be calculated at similar locations.

The design margins can be explored by increasing the thermal cycling numbers and temperature limits. However, the number of thermal cycles and temperature limits are not linear in relation to design margins. The nonlinear coefficients are different from one solder to another. If a number of thermal cycles and limits are used for comparison between different designs, the calculation becomes complicated. The easiest method is to increase the constant acceleration limit. Design margins are proportional to the constant acceleration limits regardless of what solder is used.

Special thanks to Pauline Johnson for performing many of the test coupon preparations. Thanks to Kenilee M Campbell for reviewing and editing this paper. Thanks to Ian Hardy and Rich Buck for their support of this project.