Productivity Comparison of Wafer Transport Architectures in PVD Tools Used for Fan-Out Packaging RDL Barrier/Seed Formation

The market research firms Yole Developpement and System Plus Consulting recently estimated the manufacturing cost of a single TSMC Integrated Fan-Out (InFO) wafer as ~US$500 [1]. (For comparison, we estimate the manufacturing cost of a 300mm wafer running on TSMC's 7nm FinFET process in CY2018 to be ~US$5000, given a wafer ASP of ~US$10,000 and 50% gross margin [2].)

Some of the assumptions made by Yole / System Plus to create the InFO cost estimate were the wafer size (300mm), the use of a carrier wafer (glass), the number of Redistribution Layers (3 RDLs), and the manufacturing yield (97.5%). In the breakdown of this particular fan-out packaging process (Fig. 1), the largest contributor to the total cost of a single InFO wafer is assigned to RDL manufacturing, at 34% (~US$170) of the ~US$500 cost.

If one were looking to drive costs lower for InFO then one would do well to address the RDL costs first, as they lead the Pareto analysis. (Yield loss costs come second, and will forever be the reason there are manufacturing process engineers hard at work.)

In looking to reduce RDL metallization costs, if one were to turn one's attention to other industries where the material being processed is a silicon wafer, and where metal deposition is performed using PVD systems, one would potentially learn much from the silicon photovoltaic (PV) cell manufacturing industry.

For a Silicon Heterojunction (SHJ) PV cell manufacturing process, silicon solar cells are produced from silicon wafers using a relatively simple progression of thin film deposition steps which, in one variation (PVD-SHJ), combines both PVD Cu and electroplated Cu films in the cell [3]. (Table I, and Fig. 2.)

The estimated manufacturing cost for a silicon wafer constructed with the PVD SHJ PV cell architecture shown above is ~US$1.55 (Fig. 3).

The cell production cost calculation stems from the PVD SHJ silicon PV cell having an estimated production cost of US$.31 per Watt of electrical power output, multiplied by an estimated 5W output total for one PVD SHJ PV wafer (one PV cell = one PV wafer).

From these values for PVD SHJ cell costs we can create another representation of the manufacturing cost breakdown for the silicon PV wafer, as shown in Fig. 4.

Here, it is the cost of the silicon wafer itself that dominates the manufacturing cost breakdown, with metallization being the second largest contributor. However, at US$1.55 for the total manufacturing cost of the silicon PV wafer, the metallization is only US$0.40 (i.e. 40 cents), much, much below RDL costs in fan-out packaging.

Table II summarizes the wafers costs discussed above.

These are order-of-magnitude cost differences in the manufacturing processes compared here; rather than ask how 7nm FinFET costs could be reduced to look more like fan-out packaging process costs, which would be a 10X cost reduction, maybe the better question to ask is how fan-out wafer costs could be reduced to look more like silicon PV cell costs, which would be a 330X cost reduction. And, knowing that RDL costs for the TSMC InFO process are US$170, it could be that looking to decrease those costs to be more like PV cell metallization would be a productive exercise for the fan-out packaging industry.

PVD cluster tools generally consist of some combination of three basic components or modules: vacuum loadlocks for loading and unloading wafers into the body of the system; various process chambers where unit operations for degas, pre-clean, PVD, wafer cooling, etc., are performed; and a central robot (or robots) for moving wafers between the process modules. (Most cluster tools of current vintage will also have some kind of atmospheric wafer handling system built in to address the need to “deal” wafer out of and back into the Front Opening Unified Pod, FOUP, modules in which the wafers generally live.)

This tool architecture is known as a circular cluster tool, since the process chambers are generally arranged in a circle around the central wafer handling robot.

Circular cluster tools are widely used in the front-end semiconductor industry and in the advanced packaging industry for Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), plasma etch, and for PVD processes. The quality of the process results obtained from cluster tools is generally high, meeting the yield requirements of commercial semiconductor device manufacturing and packaging, and the equipment uptime and general availability of cluster tools is also compatible with the needs of modern wafer fabs and packaging lines.

Fig. 5 shows a top-down view of several different representative cluster tool architectures.

Cluster tool productivity, however, has reached something of a limit, particularly productivity as measured in Wafers Per Hour (WPH) output, or as Cost of Ownership (COO) per wafer processed, or as capital cost per WPH.

The reason for this limit has mostly to do with the challenges of using only one central wafer-handling robot (whether single-bladed or double-bladed) to move wafers from loadlock stations to process chambers, in sequence, and then move the completed wafers back to the waiting loadlock.

Efficiently scheduling wafer movements in circular cluster tools has been a subject of much study over the years, and work on optimizing wafer movement schedules in cluster tools continues to be of great interest today. Indeed, “A disadvantage of cluster tools is that their behavior is more complex than the behavior of simpler machines. The cycle time of a lot is not constant but depends on the situation inside the cluster tool during the processing of the lot” [5].

Cluster tool throughput optimization generally requires that schedule quality be addressed for each and every process sequence running through these multi-chamber tools, and that wafer delays for each process sequence be identified and reduced [4].

In fan-out packaging, RDLs are created by first depositing a barrier/seed layer, typically composed of Ti and Cu. When PVD cluster tools are used for barrier/seed deposition, the full process sequence fan-out wafers see comprises a degas step, followed by a pre-clean step, followed by a Ti PVD step (1000Å Ti is a typical value), followed by a Cu PVD step (2000Å Cu is a typical value), after which the processed wafer is returned to a waiting FOUP.

Typical PVD cluster tool throughputs for barrier/seed layer deposition are approximately 50 wafers per hour +/− [6]. (Fig. 6.)

Despite the somewhat intractable throughput and productivity ceiling disadvantage, circular cluster tools, and PVD circular cluster tools in particular, remain the mainstay of the semiconductor front-end and semiconductor packaging industries today.

Other thin-film vacuum process tool architectures have been proposed and developed to address the throughput ceiling inherent with circular cluster tools.

Linear cluster tools consist of an array of paired process chambers along a central backbone, with each set of paired process modules attended by its own dedicated wafer transport robot, connected in a linear flow, as in Fig. 7.

The advantages of linear cluster tools include reduced floor space when compared to the number of cluster tools required to produce equivalent wafer throughputs as linear cluster tools, and also greatly simplified robot scheduling. But the very largest advantage of linear cluster tools over circular cluster tools is likely superior wafer throughput, as shown in Fig. 8.

The history of linear cluster tools in front-end semiconductor manufacturing is closely tied to efforts the industry made to transition from 300mm to 450mm silicon wafers. Linear cluster tools were going to become a “universal platform for 450mm manufacturing” [9] but, alas, adoption of linear cluster tools at 450mm proceeded about like the adoption of 450mm manufacturing itself, which is to say continuing to reside in Limbo.

Carrier-based linear transport sputter deposition systems are routinely used in the silicon photovoltaic (PV) cell industry, for example, as a result of the demonstrated usefulness of such systems in the High Volume Manufacturing (HVM) of silicon PV cells. Linear transport processing systems can also be found in industries as disparate as architectural glass production, and food and beverage processing.

The major advantage in general of linear transport (also known as in-line) process equipment, including linear transport PVD systems, is that linear transport systems essentially present a wide, continuous “sheet” of material, here wafers or panels, to the process modules; so long as product is flowing through the active process zones, the chambers (PVD magnetrons, for example) need never be turned off. This architecture goes a long way to ensuring very high system throughputs, as there is only a minimal amount of nonproductive mechanical handling overhead per processed wafer.

Fig. 9 is a top-down schematic of a representative linear transport carrier-based PVD system used in silicon PV cell processing.

Starting from the left of the diagram, silicon PV wafers are loaded (WUL/LM), transferred (TM), undergo various PVD steps (PMTCO), and are unloaded (UM/WUL). The reported wafer throughput for this PVD system is 2,400 wph.

Our own linear transport carrier-based PVD system is shown in Fig. 10.

Our linear transport sputter deposition system is capable of running >3,000wph for silicon PV sputter deposition applications, and is also capable of running the complete sequence for fan-out processing (degas – pre-clean – Ti PVD – Cu PVD) with process results meeting or exceeding the semiconductor device packaging industry's technical requirements [11]. For a typical a fan-out packaging degas – pre-clean - 1000Å Ti / 2000Å Cu barrier/seed layer sputter deposition process on 300mm wafers, the throughput of our linear transport system can be >200wph.

There are several different ways to model or represent productivity of the capital equipment used in semiconductor device fabrication and packaging. The most frequently encountered of these metrics is a general Cost of Ownership calculation, which takes into consideration a number of cost factors that are important to the operation of capital equipment in High Volume Manufacturing (HVM). There are several established commercial (Wright Williams & Kelly) or industry-consortia (SEMI) standard models for evaluating COO, and so we will start by comparing PVD tool productivity as represented by COO.

For assessing COO, we obtained system price and system throughput values for typical cluster tool systems used for barrier/seed PVD in the fan-out packaging industry. We then verified that the COO calculations delivered by our internal COO model (which is tailored to our linear process flow configuration) are the same values one obtains when using the industry-standard SEMI COO model.

Normalized COO performance, per 300mm wafer, for a degas – pre-clean - 1000Å Ti / 2000Å Cu barrier/seed layer sputter deposition fan-out packaging process, as run on our linear transport PVD system, and as run on a typical sputter deposition cluster tool used in the Advanced Packaging industry, are markedly different (Fig. 11). The linear transport system's native throughput advantage results in a much lower capital cost per wafer than the cluster PVD tool delivers, and our linear transport system's PVD magnetron delivers a much lower consumable cost per wafer than the cluster tool, with its static planar magnetron, does, as a result of the much greater sputter target utilization inherent in our magnetron design.

A second figure of merit, one coming from the silicon PV cell manufacturing industry, is to calculate raw capital cost per wafer output. The authors of [3] write: “Capital costs for the sputtering tools we reviewed were found to be on average 1573USD/(wafer/h) [28]. The total CoO of [Transparent Conductive Oxide] TCO deposition was found to be 0.087USD/wafer, of which 0.027USD/wafer (31%) was due to the consumption of ITO.” This number, US$1573/wph, agrees well with our understanding of equipment prices and system throughput for PVD tools used for silicon PV cell production.

Performing the same calculation for a typical PVD circular cluster tool used for fan-our RDL processing in the advanced packaging industry gives US$50,000/wph. For our linear transport PVD system as used for advanced packaging RDL the number is ~US$24,000/wph. (As an aside, the number for an EUV lithography tool is ~US$800,000/wph [12].)

And, finally, one may just consider raw system throughput as the important figure of merit, as system throughput itself has a large impact on wafer fab / packaging line cycle times. For a degas – pre-clean - 1000Å Ti / 2000Å Cu barrier/seed layer sputter deposition fan-out packaging process, the circular cluster tool architecture raw throughput is ~50wph, while for the linear transport PVD tool the raw throughput is >200wph. These results are summarized in Table III.

Sputter deposited Ti and Cu are the base on which electroplated copper Redistribution Layers (RDLs) are built in fan-out wafer level packaging. Circular cluster tool sputter deposition is the current Process of Record (POR) in advanced packaging for these RDL barrier/seed layers; however, these cluster systems typically operate in a regime where wafer transport is robot-limited to approximately 50 wafers per hour, which limits overall throughput and greatly influences Cost of Ownership (COO) for the sputter deposition step(s). Other wafer transport architectures, for example linear cluster tools, or linear transport PVD systems, are more efficient from a wafer handling perspective. Transport time overhead per wafer on linear transport systems can be quite low, and scheduler software optimization for linear systems is less onerous too, as a result of the simpler wafer transport architecture.

We analyzed the relative throughput of cluster and linear transport PVD tools for a typical FOWLP barrier/seed layer (1000Å Ti / 2000Å Cu) sputter deposition process. In the case of the circular cluster tool architecture, wafer throughputs are approximately 50 wafers per hour, while on our linear transport PVD system wafer throughputs as high as 240 wafers per hour are possible. The significant difference in system throughputs greatly affects the productivity returned by each system, whether productivity is measured as relative Cost of Ownership (COO) per wafer processed, the capital cost per hourly output, or the raw throughput of the sputter deposition system. The linear transport architecture produces throughputs 4× that of the circular cluster tool, has 50% less capital cost per hourly output, and achieves ~1/3 the COO of the typical cluster PVD tool currently used in the advanced packaging industry for fan-out RDL barrier/seed deposition.