Today's Through Silicon Via (TSV) processes are limited to aspect ratios of 10:1. High performance logic devices drive the need for aspect ratios approaching 20:1 in order to achieve the desired performance while simultaneously reducing costs. The reduced via area required on the wafer enables the designer to utilize less real estate on the die to reduce cost or to potentially add redundant vias to improve yield. However, current conventional processes and techniques are not capable of achieving robust fill on aspect ratios greater than 12:1. This presentation will highlight the technical challenges in achieving robust copper fill on super high aspect ratio TSV structures. Additionally, a compelling, economic solution pathway will be presented that integrates a low temperature conformal high quality dielectric isolation layer, a high step coverage Cu barrier / seed technology and a void free high speed electroplating process with a wide process window that could accelerate the adoption of the high aspect ratio TSV design schemes.

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