Processing aspects to achieve high-end hybrid backside illuminated imagers Open Access

We present a successful integration scheme of a backside illuminated 1024×1024 pixel sensor array, flip chipped on top of a ROIC with 10μm diameter Indium micro bumps, where the pixel pitch is 22.5μm. Backside illumination results, as compared to front side illumination, in a large gain in quantum efficiency because no incoming light is lost in the metal and dielectric layers. At the other side however, backside illuminated imagers requires more complex post processing because the detector array has to be thinned down to 30μm or less. Surface treatment reduces surface combination and lead to an improvement of the quantum efficiency of the device. Any damage induced at the backside of the imager is detrimental for the quantum efficiency since defects act as recombination centers for the light generated electron-hole pairs. In the end, all process optimizations on the hybrid backside illuminated imager device lead towards a quantum efficiency of 80–90% (over the visible spectrum). Next to the discussion on the critical steps (such as wafer thinning on carrier, wafer flip, cleaning), we introduce a novel backside alignment strategy to avoid using pyrex substrate as temporary carrier for thinning. Pyrex is namely not compatible in a high-end Si process environment due to its fragile nature. It is also shown that through introduction of a high aspect ratio pixel separating trenches, inter pixel electrical crosstalk can be avoided. Finally an alternative micro bump formation by means of CuSn bumps is presented.