In this paper, we propose a statistical analysis approach to consider the contributions across wide process variation permutations. The methodology is applied to a chip-to-connector high speed differential channel design for a multi-layer PCB. In addition, the contribution factor of each process variation parameter can be determined by the use of a sensitivity analysis. The DOE can be significantly reduced by over 50,000X using the Taguchi method reduction to 27. Finally, we acquire the sensitivity coefficient of each process variation parameters and probability distribution function of differential impedance, insertion loss, return loss and mode-conversion. And ±3σ impedance values were calculated and the statistical s-parameters are plotted. From these results, we can increase the confidence level of correlation between simulation and measurement because the proposed approach let us know the trend of variation of impedance and s-parameter by process variation.

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