As proliferation of handheld devices drives 3D packaging to achieve densification, embedding increased functionality into a chip is a natural complementary advancement in miniaturization. Ever increasing complexity of microelectronic design and functionality leads to the use of multiple surfaces for circuit development on wafers or individual die. Through-silicon vias, stacked die and stacked wafers, along with circuitry deposited on multiple surfaces and irregular shaped structures are some examples of 3D packaging. Laser patterning and via drilling on sapphire wafers and die with a 532 nm green laser has shown significant capabilities to make micro-features on and in the sapphire. Current structures include vias for die and wafer level interconnects, and patterned grooves for circuitry and antenna patterns. Other possibilities include pocket or trench patterning for adding passive components to the back of die or wafers. Backside patterning may be used for nano-imprinting of inks and other liquids. These grooves may also be used as micro-mixing or dispensing channels for use with nano-materials or liquids. All of these techniques may be applied to 3D die or wafer assembly and packaging.

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