Interposers: A Central Generic Technology for IoT

Internet of things (IoT) is today the next wave in the era of computing and communication, outside the realm of the traditional desktop. In this new paradigm, many of the objects surrounding us will be on the network in one form or another, with Radio Frequency IDentification (RFID) and sensor network technologies playing a major role in this new challenge [1]. Several major industrial actors strongly push the developments of these technologies (see for example [2] or [3]), and markets analysts forecast [4] high revenue generation, with 26 billion units installed by 2020. Even if most revenues will probably be generated on services [5], it is expected that many technologies will directly profit from this strongly increased hardware demand, notably in the manufacturing of innovative, miniaturized and autonomous sensors nodes. These key elemental components will be asked to measure environment parameters, process at a first level the associate information, and communicate the resulting values to the ambient network, while working almost autonomously. Integrating at reasonable cost the energizing, sensing, processing and communicating functions in a compact standardized device requires for the manufacturers to perfectly control different packaging, stacking and heterogeneous integration technologies. The optimum way to efficiently build such components, which often include different chips from diverse technologies (RF chip, MEMS chip, digital chip…) consists in using interposers on which they will be placed or stacked, depending on the final component specifications. Today, interposers are used routinely to implement many functions in efficient system-on-chip [6], offering design versatility and compatibility with die based on different technologies. Indeed, different integration schemes and stacking strategies (easier to design face to back flow, easier to process face to face flow) are today available to manufacture such systems, based on the same generic core technologies, shortly described in the next paragraph.

IoT ICs are going to be used in a very wide range of consumer products (smart watch and googles, health patches, bottle tags, etc.) used in various environments which involve among others wearable devices, flexible circuits, micro-actuators, bio-sensors. This means that in addition to traditional IC packaging specifications new constraints have to be met like flexibility, hermeticity, and/or bio-compatibility.

On the other side, a large choice of packaging substrates is today available for SiP (System in Package) IoT type devices, from renowned ceramic to laminate and new flex materials and includes silicon interposer wafers. For each of these solutions important progresses have been made recently in the aspects of integration density, manufacturability and cost competiveness, so the choice of the best solution requires a very good understanding of the packaging requirements for a given product. More specifically technical criteria as diverse as RF signal integrity, thermal management, thermo-mechanical behavior, conformability or ergonomic properties need to be considered carefully.

However silicon interposer which uses a large panel of wafer level technologies (WLP) provides a strong packaging platform to address the highest integration needs, the highest bandwidth RF communication, incomparable embedded capabilities and improved thermal dissipation in a small, thin package format. Figure 1 illustrates a silicon interposer incorporating ICs chips reported by flip-chip, μbumps and multi-level interconnection lines on front side, TSV-last, redistribution layer and solder balls for fan-out connections to BGA substrate on back side. Some features are also implemented to manage the thermo-mechanical stress at the module level and achieve a high level of reliability.

Advanced packaging technologies such as wafer level packaging are being addressed today as promising alternatives to widespread BGA flip-chip and large QFN packages and are quickly becoming a package of choice in the rapidly evolving mobile and IoT market. Moreover it is unique to achieve ultra-small form factor devices which is probably what most matters for IoT devices.

Many dedicated technological blocks have been developed in the field of 2.5D or 3D systems and are available in the main foundries worldwide. For IoT devices, the choice of the interconnection technologies is predominantly driven by the cost and the ability to high volume manufacturing.

• - TSV: technological steps for making copper filled Through Silicon Via with aspect ratios in the range 3 to 10 are today routinely controlled, with via diameters spanning between few microns to several tens of microns. Important efforts are still done to increase aspects ratios (i.e. dealing with thicker interposers) both for economical (simplifying wafer handling) and technical (low warpage allowing larger interposer) reasons.

• - Micro-bumps and micro-pillars are today the standard methods to interconnect the different die to the interposer wafer. They are generally based on Cu/Ni/SnAg solder architecture. Connections to the laminate or board are based on the same technologies but with higher dimensions. The Figure 2 illustrates the different elements of connection and the pitches for die-to-die (top) and die-to-substrate (bottom) connections.

• - Stud bumping with gold or silver even though not a wafer level processing technology.

• - Chip attach based on conductive paste, solder joint or preform, anisotropic conductive film (ACF) usually dispensed by stencil or jet printing offer attractive capabilities for larger pitch interconnections particularly with organic interposers like laminates and flex. These interconnection technologies can be used either in back-to-face or face-to-face approaches possibly coupled with RDL routing layers.

• - Routing is generally achieved with two to four layers of thick copper, either using damascene process for inorganic passivation layer, or ECD (ElectroChemical Deposition) processes for routing on organic passivation layer, as illustrated in both cases on the figure below (Figure 3).

• - Internal stress monitoring: 3D integration and TSV process require chip thinning. For the TSV mid technology or the TSV last technology, chips with silicon thicknesses below 200 μm or even below 100 μm are becoming more and more usual. In relation with this silicon thickness decrease, those chips are very sensitive to the deposited layers stress. An accurate chip bow management with temperature is then mandatory for the chips mounting compatibility and further, for the reliability during operating conditions.

• - Chip mounting based on flip-chip copper pillar technology requires a very good flatness. The thickness of the alloy used for the reflow nears 15 μm (copper pillar of 25μm diameter and 40 μm height).

• - Temporary bonding and debonding: this is an important core technology to efficiently manufacture accurate interposers in the range 80 to 200 μm. Bonding has to handle manufacturing temperature and stress as well as to comply with potential topologies. Debonding remains a critical step of the process. Depending on the internal stress level in the interposer and topology due to micro-bumps or already assembled die(s), debonding could also be impacted by the move from the 200mm to 300mm diameter. Zone bond process is now supplanting the slide-off solution to deal with 300mm wafer diameter and room temperature debonding.

• - Wafer level encapsulation: different polymer materials and techniques (pre-applied underfill, lamination, molding) are progressively introduced in the fabrication of the SiP to replace the standard packaging solutions (capillary underfill, glob top and injection molding) done at component levels.

These different items constitute the central value of the integration tool box related to interposers and 3D technologies. They allow to integrate on interposers the different functional blocks needed for IoT components.

Si interposers are enabling electrical connectivity on extremely small footprint and are of greatest interest for integrating microsensors (MEMS) in high value SiP. They may contain complex electrical paths and circuits that re-route signals from the microsystem and ease interfacing with additional components such as driver IC chip and RF communication chip. Moreover, lines and spaces are then reduced by an order of magnitude from traditional PCB. Furthermore, mounting Si MEMS (often sensitive to the stress field) onto Si interposers avoids the thermo-mechanical stress induced by a poor matching of the respective coefficients of thermal expansion of the device and the substrate.

These advantages lead today many players to develop product prototypes based on this approach, and notably in the field of RF, microwave and millimeter-wave systems with the wavelengths of the signals approaching typical microsystem dimensions.

In this context, it can be mentioned as an illustrative example the integration of an RF switch piezo electrically actuated (Figure 4) whose manufacturing and characteristics have been extensively described in [7]. The moving part of the switch is realized on a first wafer, while input pads and CPW (CoPlanar Waveguide) lines are realized on a second wafer (interposer) that includes all the DC command lines and RF routing, as well as TSVs to allow the moveable part to work in a controlled hermetical cavity. The fully packaged component exhibits both good isolation and low actuation voltage.

Other developments to integrate inertial sensors onto Si interposers can also be found in ref [8].

As stated by Yole [9] Silicon interposers are already a commercial reality in MEMS, Analog, RF & LED applications on 150mm / 200mm, supported by infrastructures of MEMS players such as DALSA / Teledyne, DNP, IMT-MEMS, and Silex Microsystems.

Industry and infrastructures are strongly interested by abandoned sensors, which can increase process control and safety at very low cost. In this new context, self-powered systems are of great value. Such systems requires energy harvesting technologies coupled with storage capabilities. Due to the actual very low power consumption of MEMS sensing devices, manufacturing of such components becomes possible. Many solutions for harvesters supplying power in the range of microwatt to milliwatt, are today investigated, based on diverse techniques (piezoelectric, electromagnetic, or thermoelectric…). In this range of energy, harvesting systems, often manufactured by micro-technologies, are small enough to be integrated on cm-sized interposers.

The same approach can be considered for the associated storage unit needed to save and manage the harvested energy: thin film all-solid-state rechargeable Li-ion microbatteries may be directly manufactured on interposers. The Figure 5 below shows examples of deposited full solid-state microbatteries integrated in diverse configurations.

With overall thicknesses in the range 5–20μ, and customizable footprint, such components perfectly fit on Si interposers for hybridization with sensors and energy harvesting solutions. Initially developed at Léti, this technology has been transferred to ST [10] and is today available at the mass production level. A typical example of demonstrator integrating thin film energy scavenging and storage components with their associated power management can be found in [11].

One of the major advantages of using an interposer approach for SIP module is the possibility to integrate high capacity and high quality passive devices (resistors, capacitors, inductance, filters, antenna …) very close to the active ICs. This can be done either by heterogeneous integration of passives silicon chip on top of the interposer using the same interconnection scheme (flip chip or others) or by embedding the passives inside the interposer itself.

In the first approach one needs to consider the passive devices post-processing for 2.5D interconnections at wafer scale to benefit from wafer level processing capability which implies to have access to the wafers. The main advantage is to use the best dedicated technology to fabricate the required passive devices giving potentially the best compromise between cost, compactness and performances.

In the second approach the integration is pushed a step further which leads to even more density. When minor added complexity in the interposer process flow is necessary for achieving the passive functions this solution can be really cost effective. For example resistors or inductances require relatively few added steps when coupled to RDL level. Yet, it is often difficult to obtain the same performances with a coprocessing approach than with a heterogeneous one.

Finally the two approaches can be advantageously combined with various passive elements on the same interposer to offer the best compromise for a given application (Figure 6) which provide a great flexibility in the architecture design.

For IOT devices, wireless communication is one of the key features. New applications such as sub-THz imaging and automotive radar are already shaping the future of the next generation of smart devices while 5G gives long term evolution (LTE) roadmap for communication of tomorrow. High data rates in the range of a few Gbps at short-range are nowadays achievable thanks to a larger RF bandwidth (up to 9 GHz for the 60 GHz ISM band). This progress has benefited from the advances in silicon-based RFIC front-end design, mostly inherited from CMOS technology which was initially dedicated to digital and low frequency analog applications. The complete TX/RX module including the digital to analog conversion, the PA (Power Amplifier) and the antenna has likely to be integrated at the chip level for optimizing the size and the performances.

However, the antenna stage's footprint is still an issue due to the fundamental relation between the radiator's effective area and the achievable gain. Frequencies corresponding to sub mm wavelengths require antenna size (λ/4) compatible in size with SiP technology, but it is known that CMOS integrated antennas-on-chip (AoC) suffer from low radiation efficiency (below 20 %).

Antenna-in-Package (AiP) approach using silicon interposer seems to be a good candidate to solve this issue: vertical stacking offers compact 3D integration capabilities as well as very good thermal dissipation properties. Moreover, using high-resistivity silicon substrates (ρ > 1kΩ.cm), radiation efficiencies in the range of 50 % could be targeted. Léti has worked on two dedicated demonstrators to assess the interest of this technology.

A first 2.5D silicon mmW demonstrator module [12] is presented in Figure 7, where a passive interposer is mounted on a PCB with Ball Grid Array (BGA) solder balls.

Micro-bumps are used to bond the RFIC chip to the interposer with a flip-chip process. In this design, RF signals are carried through front-side transmission lines to the Tx/Rx antennas while base-band signals are driven through TSV interconnects to the back side of the interposer. The radiating element is on the top side of the interposer, backed by a cavity formed by a ring of TSV, a ring of BGA solder balls and a reflector on the PCB. The antenna cavity depth is properly calculated to achieve the desired impedance and radiation properties and is defined by the interposer's thickness and BGA standoff. A WiHD (wireless HD) digital frame was successfully transmitted at 4 Gb/s net (7 Gb/s raw) over 80 cm without external amplifier between 2 modules. Heat dissipation was also measured showing good spreading effect of the silicon interposer for the flip-chipped RF IC (max temperature in TX mode measured below 55°C).

The second demonstrator [13] is based on a new type of integrated and efficient antennas. This approach aims to mimic an artificial magnetic conductor's (AMC) behavior with a near-zero reflection (at least in the frequency band of interest) allowing the reflector to be placed in the vicinity of the radiating element (from 10 μm to 20 μm at 60 GHz).

The resulting patterned structure, presented in Figure 8, is called High-Impedance Surface (HIS). This new structure allows moving towards “real 3D” integration, where the RFIC could be eventually placed directly below the antenna and fed using Through-Silicon Vias (TSV) as illustrated in Figure 9.

The 200 μm-thick interposer has been designed and micro-fabricated in CEA-Leti's 200 mm facilities. These integrated antennas have been fully characterized in anechoic chamber over multiple frequency points. The realized gain is reported for different frequency points in Figure 10.

A 5 dBi gain is achieved with excellent cross polarization isolation (−25 dB) and bandwidth (10 % using −10 dB). The achieved radiation efficiency extracted from measurement data is higher than 40% over the band of interest for HR silicon prototypes.

As already mentioned silicon technology offer unique capabilities of packaging solutions done at the wafer scale, giving extremely low profile protection and with functionalized layers. New polymer materials are also available using spin coating, film lamination or molding allowing to protect the active devices at the wafer scale and replace traditional packaging solution carried out at chip scale.

Silicon capping is used for MEMS sensors and actuators using DRIE process for the formation of the cavities, thinning and wafer-to-wafer eutectic or polymer for bonding on active wafer. This cap can be equipped with feed through via and functionalized with residual gas getters.

Thin films encapsulation on top of a sacrificial layer can be used alternately and form a protection and hermetic coating. In the case of medical application devices, very specific requirements are requested to fulfill the stringent specifications of compatibility and reliability of implanted systems. In particular, the packaging needs at the same time to be biocompatible, meaning that the human body will accept the presence of the device during its life time (or the length of medical treatment) and that the body environment (blood and bone/tissue field) will not degrade or interact with the protective layers used for the packaging.

Innovative solutions are currently developed at Leti to address this challenge in the case of silicon interposer SiP developed for cardiac implantable system to monitor the heart rate.

First, the active chips (ASIC and sensor) are bonded and interconnected on the silicon interposer wafer active face up (flip chip assembly can be also used if needed). Then a silicon wafer with cavities is bonded by AuSn eutectic joint on top of the interposer wafer to form a cap around each module. Finally a protective layer is applied all around the module (Figure 11).

Concerning the silicon cap, a special attention is requested to guarantee the hermeticity of the eutectic bonding over a lifetime specification greater than 20 years corresponding to a maximum leak rate as low as 10⁻¹² atm.cc/s. To characterize such a low leak, a residual gas analysis (RGA) with high sensitivity is used after pressurization of the module with Ar gas. After optimization of the bonding process leak rate was measured at few 10⁻¹³ atm.cc/s, validating the approach.

The choice of the final protective layer has led to the evaluation of a wide panel of materials and depositions technics reported elsewhere [14] looking for criteria of both biocompatibility and bio-stability. For biocompatibility systematic in vitro cytotoxicity tests were carried out using MDS protocol. For bio-stability, corrosion rates (C.R.) of the packaging layers in PBS (Phosphate-buffered saline) solution were studied. Among the different layers tested, it is noticed that ZnO, SiN and SiO₂ films were not stable in 37°C PBS. Conversely Al₂O₃ and TiO₂ films were found to be very interesting bio-packaging layers. Functional modules were finally delivered using this integration approach complying the requested specifications.

To summarize, wafer level packaging technologies derived in some cases from MEMS and thin film deposition can offer appropriate solutions to fabricate SiP compatible with aggressive and sensitive environment conditions found in the IOT.

Even if most revenues of IoT will probably be generated on services, it is expected that many technologies will directly profit from this strongly increased hardware demand, notably in the manufacturing of innovative, miniaturized and autonomous sensors nodes. The key elemental components require to measure environment parameters, process at a first level the associate information, and communicate the resulting values to the ambient network, while working almost autonomously. Today, the remaining challenge is to integrate all of these functions as efficiently as possible with the lowest achievable cost. Heterogeneous integration technologies, mainly based on interposers strategy and wafer level packaging solutions seem to be the best candidate to reach this goal.