A TXV-less Packaging Platform for the Era of IoTs

In the era of IoTs, more heterogeneous integration is needed. Since sensitive components such as sensor devices are included in the system, die first technology such as FO-WLP cannot be applied due to process temperature limitations and stress conditions that may alter the characteristics of the sensitive devices. Hence the die last technologies packaging methods are still in needs.

The traditional die last technology uses substrate with cores to support the packaging structure. This brings two disadvantages to the result packages. One is the addition of core structure adds additional weight and z height to the package structure. In portable and wearable applications this may not be acceptable. In addition, the through holes degrade the electrical signal integrity.

The other needs of IoT infrastructure are in the cloud end where high-end serves are been used. Advance memory platform; such as HMC, and HBM with TSVs have been proposed to be used for the next generation server. However in these applications, substrate with fine line such as 2/2 μm technology are needed that cannot be met by the current laminated substrate technology. 2.5D and 3D technologies have been proposed and developing to fill in gap of the industry. However, these solutions with TXVs are still too expensive to meet customer expectations. Innovated platform such as EIC (embedded Interposer Carrier) meets partial of the requirement (Ref. 1~3). However it is desirable to have a new packaging perform to meet the requirement of heterogeneous integration, small form factor and low cost in the era of IoTs.

As IC goes from 14/16 nm to 10 nm and even to 7 nm, more transistors are package inside one die. The die pitch needs to be decreased accordingly in order to match the high-density die. Traditional laminated substrate cannot match the fine line requirements of the substrate. Hence, packages are divided into several different levels and each level is connected by the popular solder joint method. This complicated structure is shown in Fig. 1. Advanced IC chips are connected to the silicon interposer, later solder joint connected into the substrate. This interposer with substrate is connected to the PCB again using solder joins. The interposer, substrate and PCB each has a core and connected by solder joins. This can meet the minimum system integration requirement but it is not good for the electrical signal integrity.

An innovative packaging platform without any TXVs; called eHDF (embedded high density film) is first proposed by DC Hu. (Ref. 4)

The structure used the technology from two platform processes; one used the semiconductor fine line technology and the other take the advantage of laminate large panel process. Hence the fine line, good electrical performance and low cost can be addressed at the same time by this eHDF packaging platform.

Figure 2 shows the eHDF platform structure.

Beside the benefit of no through hole and no solder joins, the Z height and weight of the package are also been reduced. In addition, the eHDF substrate is also an environmental friendly solution. Since there are no solder joins needed, it is not only a “lead free” solution but it is also a solution of “free of lead”. In addition, the overall system assembly and intermediate testing cost can also be reduced since no solder reflow is needed until the final die attach assembly.

The goals of this paper are: (1) Evaluation the feasibility of processing the eHDF structure by using the known RDL and laminated substrate technology. (2) To evaluate the chip attachment technologies of chips to the structure.

The eHDF structure composed of two portions; one is HDF (High Density Film) and the other is the incorporation of the laminated substrate.

In this study, fine line pattern were made by thin film RDL process on top of the release layer. The release layer was coated on a glass carrier. The RDL line width is 5μm with 3μm thickness. There were three layers of RDL in this study with dielectric layer thickness of 8 μm. After finished the thin film RDL process, the build-up dielectric material is laminated directly upon the thin film RDL to form the final substrate. For simplicity, three Build Up (BU) layer were used. Thickness of final substrate was about 130 μm. Finished eHDF can be released from glass carrier. And plasma clean is performed to remove the temporary bonding materials. After clean, surface finishing process of bond pad will be performed by EPIG (Pd/Au 0.06/0.1μm) plating. A 10mm × 10mm test chip could be flip-chip bonded onto eHDF to evaluate electrical performance of interconnection.

The test vehicle includes an eHDF and two 725um-thick silicon test chips were schematized in Fig. 3. Test chips were flip-chip bonded onto eHDF with capillary underfill encapsulant.

In this study, two kinds of dummy chips were applied to the test vehicle. These two dummy chips' layout mimic application processor chip and wide I/O1 memory chip as shown in Fig. 4. There were 2904 I/Os and 1675 I/Os in the AP chip and wide I/O1 chip, respectively. Chip's UBM consists of 5μm Cu, 3μm Ni and with 5μm Sn2.5Ag soldering material on top. The solder then reflowed to form micro bumps with a bump size of 18μm. The cross-sectional photo of micro solder bump structure is shown in Fig. 5.

The dimension of the single eHDF substrate was 25 mm × 25 mm with a total thickness of 130μm. 4000 I/Os of copper pad were fabricated by EPIG on the substrate with layout matching the AP chips and wide I/O chip.

Electrical performance could be evaluated with some designed RDL pattern including daisy chain, Kelvin structure. Pd/Au layer was plated on copper pads of eHDF. After bonding, Cu/Ni/Sn micro solder bumps of test chip and Cu/Pd/Au pad of eHDF would form a electrical and mechanical connections which were so called micro solder joint in this study.

K&S flip-chip bonder carried out the chip bonding with an alignment accuracy of ± 2μm. Plasma treatment was applied on the chip just before bonding. In order to get a better solder wetting of micro solder bump, flux dip process was applied in the bonding. As test chip was picked up to bond head, bump surface was coated with 6μm thick flux paste by the dip tool. After flux dipping, chip alignment and bonding were performed. Bonding mechanism had two stages, first stage was thermal compression mode and second stage adopted solder reflow mode with Z control. Temperature profile of bond head was given in Fig. 7. In bond head side, bonding temperature increased gradually and remained at 275°C for 5 seconds during bonding. Temperature of bonding stage remained at 100°C for 5 seconds. During bonding, there was an increasing force loaded on chip from 0g to 10N gradually, and then kept in 10N until the solder melt at peak temperature. As solder melting point reached, bond mode changed to Z control mode to control the stand-off height of micro solder joint to 10μm.

After bonding, test chip was peel off from the substrate and flipped to check the alignment accuracy of bonding. The initial results reflected in Fig. 8 (a) indicated these stamp of flux residue cause of bond shift. After adjusting the bonding alignment, micro solder bumps could aligned to metal pad of substrate successfully and have good solder wetting as shown in Fig.8 (b).

Some non-wetting pads were found in partial areas of substrate as shown in Fig. 8. These non-wetting pads appeared in regular pattern with shape of dimple. Compared with vacuum hole of bond tool on bond stage, we confirmed that these positions of regular dimple pattern matches to these of vacuum hole in bond tool. Based on these findings, forming mechanism of dimple on the substrate was depicted in Fig. 10. The reason of non-wetting pads are due to the physical deformation of eHDF substrate on top of the vacuum holes on the bonding stage. Furthermore, these dimple still remained its contour even though bonding temperature cooled down to room temperature. It hinted us to avoid the vacuum holes on the bonding stage.

In order to avoid the dimple issue, end substrate was attached onto a glass plate fixed with peripheral thermal adhesive tape as shown in Fig. 11. Substrate and glass were both placed onto bond stage and then bonding process could be carried out successfully. After bonding, capillary underfill (Namics 8443) was used to fill the microgap between chip and substrate and then post cured at 150°C for 30 min.

Cross-section of package was used to inspect the interconnections after bonding. The SEM photo shown in Fig. 12 presented the cross-sectional view of eHDF substrate. No delaminations or cracks were found in the substrate cross-section area. Figure 13 provided a local enlarge SEM photo of micro solder joint and presented micro solder bump had good eutectic connection with metal pads of eHDF substrate.

As chip aligned to substrate during bonding process, a small alignment mismatch was observed in monitor. This mismatch already occurred before main bond, and therefore would not cause by CTE mismatch. eHDF substrate was consisted of multi-layer organic material including thin film and build-up dielectric material. The dimension may be effected during process due to high thermal sensitivity of organic material. In order to get quantification of position variation, a high accuracy optical microscope with a linear scale was used to measure the distance shown in Fig. 14. Distance between two bump positions in four directions were measured and compared with original design specification. We found distance between two bump positions was shorter than the original design. The measuring results of AP chip and wide I/O chip were schematized in Fig. 15 and Fig. 16 respectively. Shrinkage of AP chip was about 0.08%~0.1%, shrinkage in x-direction was larger than that in the y-direction. Shrinkage of wide I/O chip was about 0.08%~0.09% and shrinkage in x-direction were similar to y-direction. Even through there were distance variation of 0.08~0.1%, it translates to substrate shrinkage of 6.5μm ~9μm. Bump size in our test vehicle was 18μm. Distance variation was a risk for bonding alignment and should be compensated in the initial design rule. After doing that, one could achieve a more accurate chip bonding results.

This study demonstrated the feasibility of both eHDF substrate process and also the assembly process of chips to the eHDF substrate. In conclusion;

A novel high-density film integrated with build-up dielectric material was demonstrated. Use semiconductor RDL process, the line/space of 5μm/5μm could be achieved.

Dimple of substrate led to non-soldering of micro solder joint due to the effect of vacuum force of bond tool stage.

Bonding process could carry out successfully as substrate attached to a glass plate without dimple formation by the vacuum force of the bond stage.

The bump position shrinks about 0.08~0.1% due to the substrate manufacture process. Even though we can achieve the bonding successfully in this study, compensation of the dimension shrinkage in the design to minimize the dimension change is needed especially for large die assembly.

Overall, the processes of eHDF substrate and chip assembly have been successfully demonstrated. We are encouraged and planning to build eHDF modules with real chip in the near future.

The authors would like to appreciate the support of Princo's manufacture team and Unimicron's NBD team and ITRI EOL's 3DIC team to realize the eHDF structure and assembly. We also appreciate the chip assembly supports from Kulicke and Soffa. Lastly, Special thanks to the Unimicron CEO TJ Tseng for his encouragement and support of this work.