This work presents the fabrication process, electrical characteristics, and circuit model of through glass via (TGV) structures consisting of TGV holes with each diameter of 100 μm and different conductors including copper and composite in the frequency range of 300 kHz to 20 GHz. The Cu/NiFe superlattice metaconductors in combination with high-quality glass (Corning SGW3) are intended to reduce radio-frequency losses especially in 10 GHz and above for next generation communication applications such as 5G communications. The measured results of the copper structure are compared to simulated results. Superlattice metaconductor results will be presented. Based on the simulation and measurement results, a circuit model is demonstrated.

Through Glass Vias (TGVs) have been a focus of research in recent years due to the lower dielectric loss and other advantages compared to Through Silicon Vias (TSVs), especially in radio-frequency (RF) applications [1]–[4]. In either case, the conductors used are predominantly pure copper for the advantages of its high electrical conductivity and cost effectiveness. However, at high frequency, the good electrical conductor does not provide as much advantage as it does at low frequency due to its skin effect, which represents the tendency of alternating current (AC) flow on the conductor surface. This results in high electrical resistance causing high power consumption in RF systems. Recently, a low loss RF conductor technology has been garnering much attention, such as a metaconductor or superlattice structure, formed by stacking alternating layers of non-ferromagnetic/ferromagnetic metals [5]–[7]. Combining the low loss glass technology and the low loss metaconductor technology would be thought to provide an ideal solution for highly power efficient RF/microwave system applications. Very recently, a few analytical lumped element models predicting single-conducting-metal TGV characteristics, TGV-TGV coupling, and even full structures have been presented, simulated, and in at least one case measured [8]–[10]. While being more practical than the structure presented in this work, the structures those authors present are somewhat limited to applications where a ground is feasible on both sides of a substrate.

In this work, efforts have been exerted to expand the work done in [11] by integrating metaconductor vias instead of solid copper vias, fabricating the vias and measuring their electrical properties, and circuit-modeling, for which some of the ideas from [8] and [9] are incorporated. Such a model might be used for applications such as 3-D interconnects and patch antennas. In fact, TGV-fed patch antennas are already a subject of research [12].

A. Theory of the Superlattice Structure

The theory of the superlattice structure deserves some discussion for the sake of explaining why there is a reduction in resistance over certain frequencies. Eddy currents generated by the non-ferromagnetic thin films cancel with those generated by the ferromagnetic thin film, or any other thin film with a negative permeability [13]. The permeability of two metal layers can be averaged to obtain an effective permeability, μeff, as noted in [14], and shown in (1). Here, tN and tF are the thickness of the nonferromagnetic and ferromagnetic layers, respectively, while μN and μF are the relative permeability of the nonferromagnetic and ferromagnetic layers, respectively.

formula

Note that when μF ≈ -tN/tF, this causes the effective permeability to equate to zero, forcing an effective skin depth [14]

formula

to equal infinity. In (2), σeff is the effective conductivity (calculated in the same way as the permeability), μ0 is the permeability of free space, and ω is the angular frequency. As noted in [5], more layers of the superlattice results in a lower resistance, theoretically reaching the value of the DC resistance. Fig. 1 shows the calculated resistance in ohms per centimeter for a 150 μm-wide stack of 10 paired Cu/NiFe layers with each pair of 150 nm/25 nm-thick Cu/NiFe. These thicknesses are also what are used in fabrication. The resistance was calculated using the iterative process in [5]. The peak is located at the ferromagnetic resonance frequency.

Fig. 1:

The resistance of the superlattice structure calculated using the iterative method. Also shown is a diagram depicting a superlattice structure.

Fig. 1:

The resistance of the superlattice structure calculated using the iterative method. Also shown is a diagram depicting a superlattice structure.

Close modal

B. Theory and Design of the Structure

A diagram of the TGV structure is shown in Fig. 2. The structure can be described as two coplanar waveguides (CPWs) feeding TGVs which are connected on the bottom by a single trace which will be called the back trace. The substrate height, h, the width of the ground traces, Gw, the center conductor width, Cw (= Bw), the via diameter, D, and the gap width, Cg, were constant across all variations of the structures made. These values, in μm, were 115, 313.8, 150, 100, and 29.6, respectively. The conductor thickness is 1.75 μm, and refers to the total thickness in the case of the superlattice structure. The values for the CPW length, GL, and back trace length, BL, are listed in Table 1. The increased CPW length was to test contact effects as well as any effects a longer CPW might have on the rest of the structure.

Table I:

Varied dimensions of the structures in μm.

Varied dimensions of the structures in μm.
Varied dimensions of the structures in μm.
Fig. 2:

Schematic of a designed TGV test structure. The structure was designed to have an input impedance of approximately 50 Ω for both ports at 10 GHz.

Fig. 2:

Schematic of a designed TGV test structure. The structure was designed to have an input impedance of approximately 50 Ω for both ports at 10 GHz.

Close modal

According to [11], this structure can be characterized using ABCD matrices representing different parts of the whole structure as well as the whole structure itself. Equations (3) through (5) show how to obtain the ABCD matrix of the TGV itself. DUT refers to the ABCD matrix of the entire structure, while STRIP refers to the ABCD matrix of the back trace.

formula
formula
formula

The model developed by [11] to characterize the TGV is a traditional pi model which assumes the parallel values on each end are the same. This is not the case for this structure. Therefore, the via is more accurately modeled by a modified circuit presented in Fig. 3.

Fig. 3:

Modified TGV circuit model based on the transmission line theory. R1 and L1 are the resistance and inductance, respectively, of the TGV.

Fig. 3:

Modified TGV circuit model based on the transmission line theory. R1 and L1 are the resistance and inductance, respectively, of the TGV.

Close modal

The analytical representations for the values in Fig. 3 are complex to find, but an ABCD matrix representation is fairly straightforward. Equations (6) through (10) detail such a solution.

formula
formula
formula
formula
formula

The results from (5) can be plugged into (8) through (10) and solved to find the values in Fig. 3. Two major assumptions are made: the vias are separated enough that there is no or negligible coupling as detailed by [9], and the interactions can be represented by a first-order lumped element model rather than higher-order models. Some components not accounted for may become dominant if these assumptions are not valid, and thereby change the equations used to obtain the lumped element values. Analytically, much of the entire structure can be accurately represented by following recommendations and formulas of [9], but by using the CPW variant detailed in [15], and for the planar structures, the inductance formulas presented in [16].

The fabrication of these structures was done on 115 μm-thick, 50 mm by 50 mm Corning SGW3 samples, where via holes were made by Corning's proprietary process. Due to the fragility of the thin substrates, the fabrication process was centered on minimizing damage and stress to the substrate. Fig. 4 shows the fabrication process.

Fig. 4:

Fabrication process: The blank area in the center of the glass represents a via hole.

Fig. 4:

Fabrication process: The blank area in the center of the glass represents a via hole.

Close modal

One way the fabrication process minimizes damage to the substrate is by doing as many processes on both sides at once as possible. This influenced how thick the initial adhesion layer needed to be, since in order to perform photolithography on both sides at once, there needed to be enough metal to block UV. 100 nm of titanium on each side has proved sufficient. A dry film (MX5020, DuPont Inc.) negative photoresist was used rather than a liquid photoresist due to the holes already present in the substrate. Additionally, it came with double-sided plastic, one side to be removed for application, and the other to be removed after UV exposure, thereby minimizing mask contamination during photolithography. The photoresist was applied slowly using a small, hard circular disk on a very flat, clean surface, and then placed on a hot plate between two flat weights kept at 95 °C for 10 minutes.

The sputter deposition of the conductor layer is both preceded and followed by deposition of a 10 nm thick titanium layer while still in the process chamber to improve adhesion. One set of copper-only structures were made, as well as a set of structures with 150 nm/25 nm copper/permalloy multi-layering to 10 pairs, totaling the 1.75 μm designed thickness. Sputter deposition has the disadvantage of being more costly and time-consuming than electroplating, but yields very smooth conductors, something that is required for a closer match to theoretical predictions, as noted by [13].

A remover or acetone is used for dry film removal. As shown in Fig. 5, the lift-off process leaves some material at the edges as the sputtering process causes side wall coverage, which would be eliminated by using an evaporation process.

Fig. 5:

(a) Microscope photograph of a superlattice structure looking down on top of the structure. (b) SEM image of inside a via from top to bottom for the copper-only structure. The slightly lifted trace edges in some areas are from the lift-off process with sputter metal deposition.

Fig. 5:

(a) Microscope photograph of a superlattice structure looking down on top of the structure. (b) SEM image of inside a via from top to bottom for the copper-only structure. The slightly lifted trace edges in some areas are from the lift-off process with sputter metal deposition.

Close modal

A. Measurement Results

Measurements of the deposited metal thickness on top of the fabricated structures are shown in Fig. 6. The difference of 0.4 μm from what was designed is particularly noteworthy. The deposition rate was lower than expected. This can be corrected by simply altering the deposition time.

Fig. 6:

Profilometer measurements of the (a) copper-only and (b) superlattice structures.

Fig. 6:

Profilometer measurements of the (a) copper-only and (b) superlattice structures.

Close modal

Frequency response measurements were performed using a two-port vector network analyzer (E5071C, Keysight Inc.) capable of outputs ranging from 300 kHz to 20 GHz. The results were put through the model presented in [11] and (3) through (10), and plotted in Fig. 7 and Fig. 8, respectively. These figures use TGV1, TGV2, and a 0.5 mm-long CPW. The simulated structure has the same thickness as was measured using the profilometer: 1.3μm. The data were run through a 5-sample running median filter to reduce some noise in higher frequencies.

Fig. 7:

Lumped element values for the shorter structures using the pi model.

Fig. 7:

Lumped element values for the shorter structures using the pi model.

Close modal
Fig. 8:

Lumped element values for the shorter structures using the model in Fig. 3.

Fig. 8:

Lumped element values for the shorter structures using the model in Fig. 3.

Close modal

It is observed that the model presented here has a slightly better match for capacitance, but resistance remains quite different. The effects of TGV-TGV coupling may account for some of the discrepancies. The high low-frequency resistance is mostly due to a thinner conductor inside the TGV, while the high frequency deviations are a combination of a thinner conductor, contact effects, and fabrication tolerance. Measurement results of superlattice structures are on-going.

The fabrication, characterization, and electric circuit modeling of an integrated through glass via (TGV) has been presented for an advanced power efficient 3-D interconnect application. A 115 μm thick low RF loss glass substrate (SGW3, Corning Inc.) has been used for high device efficiency above 10 GHz, which becomes important frequency bands for future wireless communication applications. For metallization, sputtering has been used. Although good for planar structures, sputter deposition may not be ideal for conformal coating for high aspect ratio TGVs sidewalls, for which alternative methods such as electroless and electrolytic plating, and atomic layer deposition would be investigated for future work. Electrical characterization has been performed using measurement, analytical and circuit model. Overall, the model shows good representation of the measurement results while some discrepancies have been observed in resistance, whose verification is on-going and can be presented in the conference.

This work was supported in part by the NSF Multi-Functional Integrated System Technology (MIST) center at the University of Florida. Glass substrates with vias were donated by Corning, Inc.

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