Multiphysics Performance Evaluation of Flexible Substrate Based 1.2kV SiC Half Bridge Intelligent Power Module with Stacked Dies

Wide Bandgap (WBG) power devices, especially Silicon Carbide (SiC) and Gallium Nitride (GaN), have become the most promising solution for power conversion systems with increased energy efficiency, reduced power converter size and prolonged field reliability [1]. This is due to that WBG power devices show the best tradeoff between theoretical characteristics, including high blocking voltage capability, high-temperature operation, and high switching frequencies, real commercial availability of the starting material, and maturity of their technology processes [2]. However, WBG devices are with higher cost compared with traditional Si devices. Thus, advanced power module packaging technology is being heavily explored, not only to take full advantages of the development of WBG power semiconductor devices, but also to compensate the high cost from the devices by applying cost-effective and reliable components and assembly technologies [3, 4]. Meanwhile, during the operation of power modules, the power devices are rarely the predominant failure mechanisms. Instead, the failure is usually from either the passives or the packaging [5]. The mechanical properties of power modules should be investigated in terms of long-term reliability. Also better thermal and electrical performance also need to be addressed in power electronics design.

In this paper, a specifically designed 1.2kV/40A SiC Intelligent Power Module (IPM) based on Power Supply in Packaging (PSiP) concept is introduced. The designed SiC PSiP module utilizes a recently developed epoxy-resin based dielectric as substrate instead of traditional DBC substrates.

The high power density and functionality is realized by integrating different function blocks including gate driver and isolations with the power stage. SiC MOSFETs and Schottky Diodes are fabricated with Cu as topside metallization to be solderable on double sides. No bonding wires are applied in the module. Highside and lowside SiC switches are vertically stacked on different layers for lower parasitics. CuMo spacer is applied on SiC devices for match height difference between different components.

This paper addresses performance evaluation of the designed SiC PSiP half bridge module by multiphysics simulations [6]. Q3D simulation is employed to extract parasitic parameters in the designed PSiP SiC module, and the extracted parameters are then imported in spice circuits model to simulate switching behaviors of the designed module. Thermal performance of designed module with stacked devices is evaluated by thermal simulations, and as comparison, thermal simulation is also applied on tradition module design with DBC and ultra-thin flexible dielectric as substrates. Stress induced by fabrication process is also evaluated in the designed module by mechanical simulations.

The overall analysis will figure out the weakness aspect in the design and fabrication of the module, also give hints on how to further optimize the entire performance. Most importantly, the ultra-thin flexible resin-epoxy based dielectric is initially introduced as a potential cost-effective substrate solution for power modules. The paper establishs a design guideline for power modules applying the proposed flexible dielectric.

Ultra-thin flexible dielectric has been discussed as potential substrate material for flexible electronics for a while [7–8]. Potential dielectric, suitable for power electronics applications with high power level, is also investigated in our former works [9]. A recently developed ultra-thin flexible epoxy-resin based dielectric shows its superior properties than currently available similar product, as shown in Table. 1.

The thermal conductivity is up to 8W/mK, and the dielectric can handle more than 5.6kV high voltage isolation with 120μm thickness. It can also be processed at temperature higher than 260°C, and can operate at temperature up to 200°C.

The ultra-thin flexible epoxy-resin based dielectric is available in 80μm minimum thickness. It can be bonded with Cu or Al plate on both side through a temperature profile, forming metal-clad-laminate structure. The attached Al/Cu plates can be etched into circuit layouts according to specific design, so it functions exactly as same as DBC substrates in power module applications.

The leakage current of the dielectric under 5.6kVdc at room temperature is 1nA, and even comparable with leakage of SiC device at high temperature up to 250°C. In our design, the 80μm flexible dielectric, with 70μm Cu plate on one side and 210μm Cu plate on the other, is applied.

In design, the main power loop is the half bridge topology, with a high side SiC MOSFET and its corresponding SiC schottky diode, and a lowside switch pair. Its corresponding gate driver circuits are all integrated to lower the interconnection path and improve the power density, the entire circuit schematic is as shown in Fig. 1.

High functionality is integrated in the designed PSiP IPM, Gate driver circuits are designed for each individual device pair. Bootstrap diode and capacitor are applied to provide power supply for both gate drivers. Digital isolators are also integrated for protection between main power loop and the signal from microcontroller during applications.

To further illuminate the amount of auxiliary power supplies required for this IPM, LDOs are integrated to convert the 20V power supply for gate driver circuits to the 5V for the digital isolation secondary side. The primary side of the digital isolator is connected to some terminals in the module for interconnection with external circuits, such as microcontrollers, etc.

As shown in Fig. 2 is the physical structure design of the half bridge IPM. High-side switch and low-side switch are on two different substrates stacked together, and they are electrically connected by the power terminal, locating at switch node on the middle layer. CuMo spacers (yellow) are applied on top of devices to match height difference between components on different levels. The corresponding gate driver circuits for each switch are on the same level with it. All external connections to the circuits are going through auxiliary power supply terminals as shown in the figure.

The backside of top and bottom substrate are with 210μm copper, which is able to directly attached with heat sinks on both sides according to specifically designed thermal solution. All terminals are on the same side, to make the IPM able to be placed on PCB board for system level integrations, at the same time allowing for double-side cooling with heat sink attachment on both sides. The designed SiC PSiP half bridge IPM can be applied in the system with lowest parasitics inductance and maximum cooling functions.

The SiC PSiP half bridge IPM is for high power density and high frequency applications, so the parasitic parameters are extracted by Q3D simulation results.

The parasitics have direct impact on the main power loop in power module, lower parasitics will reduce switching loss during operation, and eliminate EMI issue. To extract the parasitic inductance and resistance on the power loop, the entire two-layered IPM module is simplified and the main power loop model is as shown in Fig. 3. Only three terminals, including bus terminals, a switching node terminal are included, and power devices with exact same size of real dies on two layers.

From Q3D simulation, a current distribution is obtained as shown in Fig. 5. The current density concentrates around three terminals. This is because current is mainly flow from DC+ terminal to DC− terminal.

The parasitic inductance and resistance are extracted, as listed in the Table II. From the table, it can be found that the parasitic inductance in the entire power loop is only 1.30nH, which is among the lowest parasitic inductance value in currently available developed half bridge module.

The parasitics have impact on circuit operation, especially switching behavior. To evaluate the circuit performance, the extracted parasitic parameters are imported into the spice model, as shown in Fig. 6.

The switching waveform on the lowside SiC MOSFET is as shown in Fig. 7 and Fig. 8.

In the simulation, the bus voltage is set as 1000V, and targeted current rating is set as 32A. According to the waveform, only limited ringings appear in the current and voltage waveforms, which is less than 2A for drain current and less than 50V for Vds. The design with ultra-low parasitics improves the performance of SiC PSiP half bridge IPM.

To evaluate thermal performance of the flexible dielectric substrate based SiC PSiP half bridge IPM, different models are applied for comparison, including planar module structure with DBC as substrate, planar module with ultra-thin flexible dielectric as substrate, and the designed IPM with stacked dies, as shown in Fig. 9.

All the substrate size is the same except thickness, the designed module is for 1200V applications, so DBC with 5mil Cu and 10mil ceramic is applied as shown in Fig. 9(a). The planar module with ultra-thin dielectric applied 80μm dielectric with 70μm Cu on one side and 210μm Cu on the backside, as shown in Fig. 9(b). As shown in Fig. 9(c), the substrate size is as same as model (b), CuMo alloy is applied as spacer in the model to match height difference, and for better thermal performance. The thickness of solder layers attached to devices and corresponding spacers are all kept as 50μm. In model (a), different ceramic material is applied on the DBC substrate, including alumina and aluminum nitride, and ultra-thin dielectric as comparison. To compare thermal impedance with different substrate and module design, bottom temperature is set as 298.15K. The power consumption on each SiC MOSFET is 24W, and on SiC schottky diode is 4W per device. The simulation result is as shown in Fig. 10.

The junction temperature for module with alumina DBC substrate, 307K, is close to that of ultra-thin dielectric substrate, 308K. It indicates ultra-thin dielectric based Cu-clad-laminate substrate has comparable thermal performance with alumina based DBC substrate. The junction temperature in module with AlN DBC is 302K, due to high thermal conductivity of AlN.

The same boundary conditions are applied on the designed IPM with stacked structure. Simulation results, as shown in Fig. 11, show that the junction temperature is 361K, much higher than those of models as shown in Fig. 11. This is because thermal fields built by power generated at both SiC MOSFETs are over-lapped in the stacked structure.

In real case, module bottom is attached to baseplates and heatsinks, the temperature cannot be fixed and uniformly distributed. Considering maximum temperature on module bottom is around 80°C, and assuming different heat dissipation technologies can be substituted by convection coefficient applied on module bottom, it was found that 3000W/m²K can get temperature distribution close to real case, as shown in Fig.12. Maximum temperature at bottom of each model is around 353.15K to 363.15K. Module with AlN DBC shows lowest junction temperature, while the other two show same junction temperature.

Different convection coefficients, from 3000W/m²K to 6000W/m²K, are applied on both side of substrates in the stacked IPM model, as shown in Fig. 13.

As bottom convection coefficient increases, junction temperature of the designed SiC PSiP half bridge IPM decreases. When convection coefficient is 3000W/m2K, the junction temperature is 385K, 22K higher than planar module with the same substrate. When convection coefficient on both sides of the SiC IPM is doubled, the junction temperature can be even lower than that in planar modules with AlN DBC substrates. The SiC PSiP half bridge IPM, with stacked dies, requires specifically designed heatsink to have comparable junction temperature with planar modules.

During fabrication processes, such as reflowing process, thermal-stress will be induced into power modules. In the designed SiC PSiP half bridge IPM, a new dielectric substrate is applied as substitute of traditional DBC substrate. The pre-stress analysis is applied to compare mechanical performance of two substrates, 80μm flexible dielectric with 70μm Cu pads on one side and 210μm Cu pad on the other, and 254μm alumina DBC substrate with 127μm Cu pads on both sides. The models of two modules, marked as A (alumina DBC substrate) and B(80μm flexible dielectric based Cu-clad-laminate substrate), are as shown in Fig. 14.

The model is based on general phase leg module design, on the same Cu pad is the switch pair including a SiC MOSFET and a SiC schottky diode. Only half of the entire model is established, and symmetric boundary condition is applied as shown in Fig. 14.

Solder material is Sn63Pn37, with melting point 183°C, in the model. To analyze pre-stress from reflowing process, the temperature loaded on the model starts at 180°C, and decrease to 25°C in 160s, and dwells for 40s.

The von-mises stress distribution in different models is as shown in Fig. 15. In the module with DBC substrate, the maximum stress locates at corners of top Cu pads, but maximum stress in the other module is at corner of bottom Cu plate. Higher maximum Von Mises stress is in module A, 374MPa, than module B, 139MPa. Module B has more stress, up to 77MPa, on SiC devices.

Stress on different layers, including solder layer, top Cu pad layer, dielectric layer, and bottom Cu plate layer, are also analyzed as shown in Fig. 16–19.

The Von Mises stress in Module A solder layer distributed evenly on topside and bottom side, with maximum value, 20.9MPa, at far end corners. The maximum stress on solder layer in module B, 18.2MPa, is mainly on corners of interface with SiC MOSFETs.

The maximum Von Mises stress, 374MPa, on top copper pad in Module A is located on the far end corners at the interface with alumina. The maximum on top copper pad in Module B is located beneath SiC device, with maximum value 108MPa.

Dielectric layer, both material are brittle materials, first principle stress is analyzed. The maximum stress in Module A at alumina layer is 243MPa, located at the interface with Cu plate on the bottom. For module B, the maximum stress, 50.1MPa, on dielectric layer is at the interface with copper plats on both sides, under the region with SiC devices.

The maximum Von Mises stress on bottom Cu plate in Module A is 215MPa, located on corners at the interface with alumina ceramic layer. For module B, the maximum stress, 139MPa, is located at the interface with dielectric, but the area surrounding SiC device regions.

According to the analysis, Module A has higher maximum stress at each layer, than those of Module B. And the maximum stress located at the interface between Cu pads and dielectric layers. In terms of pre-stress, the ultra-thin flexible 80μm epoxy-resin based dielectric can provide better mechanical performance in power modules than traditional DBC substrates.

The paper introduces a design of 1.2kV SiC half bridge IPM based on Power Supply in Package concept. Stacked Structure is firstly proposed in this work to vertically connect highside and lowside SiC switches. A recently developed ultra-thin flexible epoxy-resin based dielectric is introduced as substrate materials in the designed module.

Q3D simulations prove that the design has ultra-low parasitics, even less than 1.5nH on the power loop. Double pulse test circuit with and without extracted parasitic parameters are applied to simulate switching behavior of the designed module with stacked dies. Only a small amount of overshoot and ringing happens during switching in the designed module.

Thermal simulation compares junction temperature of different models with various types of substrates. The designed SiC half bridge IPM has higher junction temperature, but with specifically designed heat sink, its junction temperature can be lowered to the value comparable with traditional power module design.

Mechanical simulation compares pre-stress in modules with alumina DBC substrate and ultra-thin flexible dielectric substrate, and proves that by applying ultra-thin flexible substrate, maximum stress at each layer in the module can be significantly reduced.

This work initiates investigation on 1.2kV PSiP based SiC IMP with new substrate material and innovative structure design for ultra-low parasitics. The paper verifies the improved performance in the designed module, in terms of parasitic parameters, switching behaviors and mechanical stress. A guideline on heat sink design to improve thermal performance of the designed PSiP based 1.2kV SiC half bridge IPM is also provided.

This work was supported, in part, by a grant from Texas Instruments, under the direction of Dr. Luu Nguyen. A special thanks to Risho Kogyo Co., Ltd, for their tremendous support on the unique material.