“A Cross-Domain, System Planning Methodology” Open Access

Holistically planning and optimizing the complete SoC, package (SiP) and board “system”, will produce designs with ideal floorplans, pin-outs, and component placements. These optimized designs/layouts will require fewer routing layers - drastically reducing cost and less human interaction (domain experts) to complete - drastically reducing design cycle time and minimizing human interaction.

We propose a methodology to look at the different design domains as an overall system, plan the system at a higher level of abstraction, and then push the planning results into the implementation tools.

Designers now, more than ever, need a tool that allows the designer to evaluate the entire system, identify opportunities for optimization (in both partitioning and assignment), and to drive those updates into their respective design domains. This means they must have the ability to access and modify the die driver placement, set bump placement and assignment, package ball placement and assignment, and establish interconnect between the two. Providing a tool that allows the designer to see the physical extents of the drivers, the die and the package or packages (possibly interposers), and a printed circuit board allows them to look at the entire system, optimizing placement and assignment. At this representation level, they do not need all of the constraints or detailed routing and can assess the design in a simplified state.

Once the overall system is planned at a high level of abstraction, the design can then be formally transferred over to the implementation tools using proper design format. Depending on the hierarchy of the design, this could be a single database, or it could be multiple databases in multiple tools. The system design moves from a high level of abstraction to the more detailed substrate and die implementation views. Here, the additional routing and manufacturing constraints can be applied and a more precise level of co-design can be leveraged. The designer now focuses on the detail of the interfaces between individual parts of the system and not the entire system. This includes tasks like swapping driver placement in the die, differential pair assignment, or bump to ball assignments in the package necessitated by the additional, more detailed design constraints.

Leveraging both system-level path-finding and cross-domain co-design can ease the burden of complicated system requirements. Providing a multi-fabric view in a single canvas, allowing the designer to optimize interfaces in the context of the entire system early in the design process, and then moving that design into the implementation tools and leveraging cross-domain co-design to optimize the package and the IC layout eases the restrictions imposed by large designs. The designer can reduce the overall layer count, run advanced DRC's and leverage technology-driven capabilities within the implementation tool to meet the stringent requirements of the manufacturer. The benefit is increased design efficiency, and a reduction in overall design cycle-time, while maintaining the desired performance of the system.

The days of working on isolated design Islands are clearly at an end. No longer can each of the design teams (IC, package and interposer, PCB) work in an isolated environment and maintain any level of efficiency. The package designer, in the center of the design process, must look beyond the simple connections to the adjacent design domains to generate a design that is cost-effective, meets form factor requirements, and meets the signal Integrity requirements of the entire system. There are really two opportunities for the system designer to work in a common and collaborative environment: cross-domain system planning and optimization up front in the design process, and opportunities and capabilities to co-design between adjacent domains as the design team moves into the implementation process.

Let's look at “up-front” system planning first (Figure 1). A system designer or design team has the opportunity to perform initial planning early in the process before the respective domains start the implementation process. This is not a new concept, and it does not take a lot of sophistication to do some level of initial planning even if it's on the back of a napkin. However, providing a formal tool and a methodology to extend that simplified used-model to a formal planning process can yield significant rewards and time-saving. If a company's vertical design team, or the design team working with their external suppliers can leverage this capability, it can lead to reduced layer-count, optimized performance and possibly the difference between meeting the cost and time targets for the design. Due to the complexity of the overall design and the number of signals being considered, many designers may spend less time performing classic layout and routing operations and more time on the initial planning and partitioning of the connectivity of the design prior to the actual routing. This upfront planning investment allows the designer to shorten the time spent at implementation.

The system designer, or system design team, can look at all three domains at once. There is now an opportunity to consider the placement of the I/O blocks in the pad ring of the IC, the connectivity between the ring and the bumps or wire bond pads, the interconnect and placement in the package, and the partitioning of the system between a few SOCs, and interposer or many chiplets in a heterogeneous design. The system planner has the full scope of the design at their disposal to develop an implementation plan optimizing the goals of the design. Likewise, the system designer can look at the partitioning of the substrates whether it be a single package, package-on-package, and optimize their footprints within the context of the PCB. At this higher level of abstraction, the system designer can plan out the overall design both from a physical layout perspective as well as perform initial SI simulation to ensure that buses and critical signaling in the design meet the requirements. The hierarchical net-naming across the different domains can be established and maintained as the system is organized (Figure 2).

The system designer should have a mechanism that allows him to look at and manipulate the system at this higher level of abstraction. It may be sufficient to work with simple outlines and connectivity locations, and the interconnect between them as simple flight lines or trial routes. They can establish multiple scenarios of how the system might be partitioned and laid out in the IC, package substrates, and the PCB (Figure 3).

The designer can consider those entities that are fixed and constrained and those entities that he has control and freedom to modify or create to meet the design constraints. The system designer can look at placement, orientation, partitioning, signal interconnect path and escape ordering, and early constraints to create a high-level view of the entire design. They should have the ability to access and modify the die driver placement, bump placement and assignment, and the interconnect between the two. Likewise, the point-to-point connections and the logical bus grouping, the package ball placement and assignment for routeability, and the interconnect with the PCB can all be modified (Figure 4).

Having a tool at their disposal that allows the designer to see the physical extents and approximate sizes of the die in the package or packages and the underlying printed circuit board allows them to consider the entire system and to optimize both the partitioning and the physical placement. At this level of abstraction the system design team does not need very specific details but a simplified view that can be used to do place buses on adjacent sides of multiple die, or the same side in a stacking arrangement. They can plan, group, assign and connect the various interfaces. Large buses can be treated as a single path entity with the detail of their signal members only represented at the ends simplify the view, yet still manipulate the signal sequencing to reduce layer count (Figure 5).

Given sufficient freedoms, the designer can make pin assignment swaps within a bus, and manipulate the escape sequence that may allow it to be routed in a single layer, even in a complex design. This portion of the design phase can either be a feasibility flow where the design team determines whether it is even cost-effective or physically possible to build the design with the existing manufacturing technology, or the design has to be implemented, and we are doing this analysis to meet all of the design constraints (cost, form-factor, signal integrity).

Once the overall system is planned at this higher level of abstraction, the routing studies have been done, and the initial signal integrity assessment has been completed and the design team is confident that they can meet their targets, the team can then transfer the design to each of the respective implementation tools. Depending on the hierarchy and partitioning of the design this could be one database or many databases. Unlike the proverbial “back-of-the-napkin”, the portions of the design can be moved over to the implementation tools with no loss of content. The respective design teams can now focus on the detail of the interfaces between the parts of the system and the individual substrates or die. The design team converts the simplified versions of the design to formal implementation and does so, not in a vacuum, but with a sense of the overall system.

This brings us to the second large opportunity to maximize the design. Given the initial settings and locations from the system planning phase, they must now worry about the routeability, layer count and meeting signal integrity and power Integrity requirements within their respective domain. For some, they can complete this with no further interaction with the other teams; the likelihood, however, is that there will be changes, driven from any one of the design domains that have to be accounted for in the overall system. The designer may have no option other than to modify the footprints, swap signals, or optimize the interconnect. It is therefore beneficial if the designer can co-design with whichever domain owns the other end of the change.

Co-design is not a new or a unique concept. Design teams can sit collaboratively with designers in other areas of their company or with other vendors. However, the ability to do so with an EDA tool that understands the constraints of each domain and allows the design teams to negotiate and try different proposals to optimize the design is critical. For years, designers have used various techniques to suggest, plan and confirm design changes between the different domains, using either manual documentation, email, spreadsheets (cell-based footprints), ASCII files, and other various data exchange methods. Unfortunately, these methodologies can be tedious, uncontrolled an error-prone. There is an opportunity for data and communication to be lost, modified, improperly represented, or done out of sequence (e.g. standardizing and maintaining the orientation of a bump or ball map relative to its placement orientation in the overall system design.

It is far better if the respective domain tools can facilitate the negotiation by using standard formats and capabilities that are designed to enable this collaboration. Co-design includes adding or subtracting connection points, manipulating the location of those points and the assignment of those points, whether they are a driver pin, bump, or ball. Doing so within a framework that enables collaboration and protects the integrity of the design with standardized formats that both tools in the exchange understand is a key contribution from EDA vendors (Figure 6).

Likewise, it is relatively rare to find individuals that are experts in more than one domain, and the EDA tools can allow two experts to clearly negotiate a change. EDA tools provide a formal mechanism to suggest and confirm these changes in an orderly, tracked and controlled manner.

Once the interconnect is optimized and approved on both sides the designer can then focus on meeting the manufacturing design rules required by the foundry, OSAT or PCB manufacturer. A full suite of tools and constraints can be implemented to ensure that the design meets the manufacturing capability and yield of the respective manufacturer.

Our discussion has focused on mostly physical implementation, but clearly, that is not the only benefit of upfront system planning and co-design. At any level of abstraction, some form of signal and power Integrity analysis can be done, the accuracy of which depends on the level of detail in the design. Providing a mechanism to evaluate the design even at an abstraction level ensures that the designer does not make layout mistakes early in the process. Early evaluation and assessment ensure that any issues are identified early and changes made such that the impact in the implementation phase is minimal. As the design progresses and we transition to making changes by co-design; we now have a more exact version of the layout that can be run with stricter criteria and more elaborate analysis. Through these iterations, the design team can converge on a design that meets electrical requirements as well as the physical with minimal disruptions.

By enabling upfront system planning as well as providing a mechanism for the implementation teams to suggest changes to optimize the design, the design team can converge faster on a system design that meets all requirements. Upfront planning prevents large re-work changes late in the design process. Co-design enables changes that must be done but does so in a controlled methodology to the user.