Recess in the motherboard architectures for small form factor systems Open Access

As electronic devices grow in complexity and functionality they are also becoming smaller, thinner and more integrated. This combination, along with the continuous drive for cost reduction, creates a myriad of new challenges for surface mount and other board assembly processes. The common technique of placing small components on the land-side of a Ball Grid Array (BGA) package substrate has become especially challenging since the gap between the package and motherboard is shrinking faster than the components themselves. During the SMT reflow attach process, interference between the mother board and land side package components (LSC) can result in poor joint formation and low yields [1–3]. To minimize interference, it is typical to create a hole in the motherboard or to move the LSCs to another location. Both solutions can result in cost or performance issues. Another solution, described here, creates a controlled-depth recess by removing a predetermined number of layers in the motherboard directly under the LSC's on the package. This allows the components to sit in this recess without impacting the surface mount process. This recess-in-motherboard (RiMB) architecture enables increased density of functional components (voltage regulation, passives, EMI shielding) for next generation mobile products with minimal cost or performance impact.

This paper describes the basic formation of the recess architecture and provides design guidelines used to define x/y size and depth. The recess depth is the most influential attribute. A full section of this paper is dedicated to calculating the optimal depth. One section covers measuring this depth. Further, this paper explores SMT risk and presents assembly yield from test vehicles and functional devices using the RiMB architecture.

Recess in motherboards require a clear design trade-off. Shallower recess designs allow for more routing layers to remain in the final motherboard. Deeper recess designs allow for more manufacturing variance before the occurrence of an interference between the LSCs and the printed circuit board (PCB). Striking this balance requires an understanding of manufacturing methods and variables as well as an appreciation of how to control them.

Figure 1 shows a bare PCB with the center region recessed to allow for adequate clearance of the package LSCs.

The fabrication and assembly of the recess needs to account for specific design features and their respective dimensions and tolerances. Focusing on the PCB, the outer most layers may require a setback of solder mask from the recess edge to avoid damage. The solder mask (SM) registration values will drive minimum design targets. Adequate inner layer copper setback to the recess wall ensures there is sufficient dielectric to prevent etch breakout and delamination along the side wall. The outline of the recess may require controls of corner radii. The radii may require larger dimensions to support mechanical processes where a minimum drill radius may be needed to support high volume productions.

Figure 2 is included as a starting point for these PCB key design attributes and provides our forecast of their progression over the next few years. It is important to establish this set of design guidelines with each PCB fabricator. Detailed dimensions along with tolerances that are in line with PCB fabricator methods are important to guide PCB design. The design guidelines will translate to route and via keepout zones.

No industry standard exists for the creation of a recess into a PCB. Therefore each PCB manufacture often finds a unique processing flow to create these features into the final design [2]. However in our work to-date we have found two general approaches are used. The first is utilizing a controlled depth drilling step to remove the PCB material in the recess area. The second uses a laser drilling tool to either ablate the recess material or cut enough of the perimeter material to allow for extraction of the remaining plug. Below we outline the basic manufacturing aspects and compare differences as they relate to the final recess.

Each PCB manufacturer will have a specific process flow. In general, the controlled depth routing step is performed in company with the final route and score drill steps. The board cannot be stacked and must be processed in a sequential flow. Figure 3 outlines an example of the mechanical method.

In this step, the drill bit routes out the recess shape. Per the design notes outlined in Figure 2, drill bit size and corner radii are considered to allow for a drill of adequate diameter. Depth is controlled with electrical and/or force feedback depending on the tool and depth tolerance. Based on the drilling tool and processing methods (like chuck calibration and mapping), a recess depth tolerance of ±0.030mm may be achievable on small batches. However, with lot-to-lot variance and more importantly beat-rate as it impacts cost, a depth of ±0.020mm is common for Figure 3.

Again it should be noted that each PCB manufacturer will have a specific process flow. In general, laser ablation is performed as one of the final processing steps. In place of a controlled depth mechanical drill, a laser drill is used to cut, and stopping on a copper (Cu) feature internal to the PCB. The Cu feature can either be a solid shape allowing for the laser to ablate 100% of the recess material or a perimeter Cu laser feature allowing the laser to outline the recess plug. A subsequent processing step can extract the inner plug assuming the PCB manufacture applied a release layer at its base. Each PCB manufacturer applies some variation to these two general flows, and can best describe their specific methods. Figure 4 outlines an example of the laser ablation method.

In this step the laser will be able to cut only to a depth that matches an internal Cu layer. While limited to fixed Cu depths, the laser method often provides tighter tolerances when compared to the mechanical methods. The laser ablation will always terminate on the Cu surface such as layer 4 in the figure above. Depth tolerance then becomes driven by the variance of where layer 4 physically sits in the board construction. In our application of a recess where the target depth is approximately 0.200mm, the recess depth tolerance of ±0.020mm may be achievable on small batches. However with lot-to-lot variance and more importantly beat-rate as it impacts cost, a depth of ±0.050mm is common for Figure 4.

Table 1 provides a qualitative summary of manufacturing aspects of the two common methods.

Depth of the recess must be balanced. Removing too many layers limits the recess value for routing in the remaining layers. Removing too few layers induces a manufacturing risk for an interference to occur between the packaged part and the PCB. This section will cover the major variables and provide a root-sum of squares model to guide users in trading off the key variables. In our experience the potential for package to PCB interference is most pronounced during the SMT reflow process. Therefore we will simplify the analysis to this specific case.

Key variables are the package variance, post SMT ball height, motherboard flatness, and the RiMB depth. Figure 5 illustrates these four variables.

Package variance is driven by the package shape before and during reflow combined with its components such as land side capacitors. Post SMT ball height is driven by the package solder ball size, SMT paste volume, and collapse during reflow, when the ball melts and coalesces with the molten solder paste. Motherboard flatness is driven by PCB material selection, PCB size, and Cu density differences between its layers. Motherboard flatness needs to be characterized at the peak reflow temperature accounting for any changes due to the heating. Finally, the RiMB depth is a function of the PCB fabrication aspects as outlined in section III.

Pulling these variables into a calculator (Table 2) allows the designer to understand how important it is to consider their mean as well as manufacturing tolerances.

The calculator provides the nominal mean (0.070 mm) of the interference risk between the package bottom and the top of the motherboard's recess area. It also tracks the standard deviation of each variable. To quantify the risk, we calculate the interference risk as opportunities per million (IR/M) for these two surfaces to make contact and interfere.

The nominal mean is the sum of the variable means as noted in equation 1. The standard deviation is the sum of squares of the 1-sigma tolerance for each variable. The IR/M is calculated as a probability density function (equation 2) express it in opportunities per million. To fully grasp the total risk, IR/M is expressed as the cumulative distribution function.

To better illustrate this risk, three set of values are considered below. In Table 3 the first sample set would hold the motherboard flatness and recess depth tolerances at ±0.050mm for their 4σ range. This generates a risk of 755 chances in 1 million for an interference. The second sample set would hold the motherboard flatness and recess depth tolerances at ±0.075mm for their 4σ range. These larger tolerance ranges may allow for a lower cost MB, it increases the risk to 9060 chances in a million for an interference. The third set would tighten the motherboard flatness and recess depth tolerances at ±0.030mm for their 4σ range. This tighter tolerance would require more screening and may drive processing costs up, but it reduces the risk to 14 chances in a million for an interference.

Figure 6 illustrates the sample interference (distribution functions) described above. When plotted it shows the importance of understanding the full processing range for each of the variables. Even with equal nominal designs allowing for 0.070mm of gap on average, changing the distribution introduces the different level of manufacturing risks.

Figure 7 is the same graph as Figure 6 but with a different scales to show the tail of the distributions. When dealing with high volume builds its key for the designer, PCB fabricator, and PCB assembly house to understand their impact when designing a RiMB.

Since no standard exists for defining a good recess, it's important for the designer, assembly house, and PCB fabricator to agree on what, where, how, and how often boards need to be measured. In work to date, we have found two methods work best for measuring the recess depth and its topology. First is a cross-section. While it is limited to a single plane and is destructive, it aligns with the common metrology tools at both the PCB fabricator and assembly house. The second method is a non-contact optical coordinate measuring machine (OCMM). This method requires more time to program, but allows for a full recess topology and its automation allows for a larger sampling to study lot-to-lot variances [4]. We will focus on the OCMM for the remainder of this section.

General steps are as follows. Step 1, select the reference pads and recess points to be measured. Step 2, extract the reference pads into the OCMM using appropriate software. Step 3, Alignment. Step 4, establish a Z-plane as close to the recess measurement area. Step 5, measure the pads and recess points. Step 6, Data analysis.

In our experience it's best to sample points along both the horizontal and vertical centerlines of the recess. Figure 8 shows a graphical representation of the sampling points. At this time, we sample along the center lines as well as in each quadrant of the recess.

We apply a simple difference between the PCB surface pads (shown in red) and the recess points (shown in orange). For a given product we monitor for the minimum of this dataset since this is what's used in the interference calculator in Table 2 above.

To evaluate the interference calculator and the solderability risks of the LSC interference with the recess when using RiMB, a number of controlled units were designed and assembled. These units were 28mm × 16.5mm × 1.04mm BGA packages that consisted of 1392 228um diameter BGA spheres spaced at 0.43mm pitch. The land-side of the packages each contained 73 XLP passives that have a nominal stand-off height of 236um. The BGA packages were assembled onto three sets of 10-layer test boards designed to 0.60mm, 0.66mm and 0.80mm thick. Each board was manufactured with three locations to place the BGA packages, as shown in Figure 9. Uniform, 10 mil bonding pads are used at all locations. The recess creation in the boards used both the controlled depth and the laser drilling technique as discussed previously and recess depths were nominally designed to 145um, 160um and 230um in order to test the interference risk at different depths. Prior to SMT, the package and board warpages were measured and characterized to determine flatness variance. The recess depths were measured using the OCMM method described in section V. The BGA devices were surface mounted to the boards using standard SAC 305 solder paste. The paste was applied using 100um thick stencils with 254um solder paste apertures resulting in a final solder standoff height of 170um after SMT.

For this study, 156 units were assembled and inspected using 3D X-ray to determine solder joint quality. Further, a sampling of units were cross-sectioned to characterize the solder joint microstructure, the post SMT ball height and the final gap distance between the land side caps and the recess surface. Based on these measured values, an interference prediction (IR/M) was generated. Table 4 shows the calculated probability of interference as well as the final LSC-to-recess gap measured by cross-section and the SMT yield. In all cases, there were no observation of shorting or bridging during SMT as measured by X-ray analysis, and cross-section images showed no instances of the land-side passives contacting the recess. This is consistent with the calculated values for all data sets based on the characterized depth, variance, and flatness of the recessed boards.

Based on the sample size and the tolerances in the board and package warpages during reflow, it appears that the Interference Calculator gives a reasonable estimate of the final gap height and IR/M values and provides a useful tool for board designers developing RiMB architectures.

Recess in motherboard requires more design focus to balance assembly risk and recess depth. This work presented an interference calculator that can be used to balance the design and assembly risks by quantifying an interference of land-side components with the bottom of the recess. The formation of the recess by the PCB fabricators must also be well understood. The two most common methods to manufacture RiMB are mechanical routing and laser ablation. Even within a method, each fabricator will generate different final depths depending on their process flow. To properly monitor and feedback the process tolerance, cross-sections and OCMM metrologies were discussed to measure recess depths. Lastly, this study evaluated PCBs with different thicknesses and recess depths and showed that the air gap of landside components on the backside of BGAs that placed on the PCB during the SMT process, and the bottom of the recess were consistent with the calculated air gap values.

The authors would like to thank many contributors to the work presented here. Carlos Mariscal and Wes Roth spent countless hours designing our 20 plus test boards over the past 2 years. Todd Harris and Morgan Tribolet ran dozens of SMT experiments collecting thousands of package results. Pubudu Goonetilleke led our FA group investigating anomalies in the SMT and assembly data. Dungh Nguyen collected and analyzed hundreds of recess PCBs at our incoming inspection to evaluate suppliers and segment boards for various experimental legs. And finally we would like to thank Raiyo Aspandiar and Brett Grossman for their coaching and feedback on this paper.