Universal Connection Matrix: A Breadboard in a Package

As Moore's Law approaches retirement age[1][2], the technological advances wrought through the improvements in silicon process technology are staggering. These process improvements have allowed silicon processes to be tailored for specific components such as power electronics (i.e. a high power, high voltage, low density, low frequency process), sensors and analog components (i.e. a low power, high voltage, high density, low frequency process), RF circuitry (i.e. a high power, low voltage, low density, high frequency process), and microprocessors and memories (i.e. a low power, low voltage, high density, high frequency process), see Figure 1. This has enabled the proliferation of technology and new business models in the age of the Internet of Things (IoT).

However, for all the advancements in silicon process technology, each component can only have one silicon process. Therefore, while a System on a Chip (SoC) can integrate many different functional blocks, such as a processor, memory, power converters, RF circuitry, sensors, and analog components, it fundamentally requires a compromise. Instead of building each functional block in its most optimal silicon process, all blocks within an SoC must use the same process, see Figure 2. This compromise has led both to a loss of process entitlement, in that not all functional blocks within an SoC can scale with process, as well as a loss of performance.

Where Moore's Law left off from the perspective of the individual component, packaging technology has taken up the reigns. Packaging technologies are now able push the boundaries of form, fit, and function beyond that which is possible with SoC technology. Systems in a Package (“SiP”s) can enable new levels of integration and size reduction for embedded systems[3][4]. However, like the technologies that have come before it, SiPs require enormous investments of design time and effort. In this paper, we introduce the Universal Connection Matrix (UCM) which allows for faster design and prototyping with SiP devices. Instead of large, monolithic designs, the UCM provides a breadboard in a package.

In the silicon industry, there is the fundamental drive to integrate more and more of an embedded system into a single component. This allows for faster, wider, lower power interconnects between components, smaller footprints, and easier development processes for system designers. Single fixed-function Application Specific Integrated Circuits (ASICs) have given way to System on a Chip (SoC) devices for most embedded system applications. By incorporating many different functional circuit blocks, including both analog and digital circuits, on a single monolithic block of silicon, SoCs make designing an embedded system easier. Instead of connecting hundreds or thousands of discrete components together on a printed circuit board (PCB), a single SoC can fulfill much of the system needs.

Similarly, a chip package has historically been a single fixed-function device to provide access to the silicon device inside and to help with thermal management. As processors needed tighter integration with passive components and memories, Package-on-Package (PoP) and Multi-Chip Module (MCM) techniques started to appear. Today, with the development of advanced packaging techniques, SiP devices are now able to integrate multiple silicon devices alongside packaged devices and passive components on a single package substrate, see Figure 2.

The resulting package substrate has become a miniature printed circuit board, see Figure 3. SiPs enable all components of an embedded system, such as digital devices, analog circuits, memories, sensors, power management, and wireless devices to be integrated together into a single component. These components can have diverse fabrication technologies and might otherwise be impossible or impractical to integrate together into a single block of silicon.

However, similar to SoCs, there is an up-front design cost to develop the SiP substrate. A SiP substrate design contains elements of both a printed circuit board and an integrated circuit. Like a custom PCB, a SiP substrate requires schematics and layout with electrical simulations for all high-speed busses. For example, the connections between a DDR memory and a processor must be length matched, impedance matched and simulated to ensure proper timing and electrical connection. Like an IC, a SiP substrate is tested using a standard IC manufacturing flow and as such requires a load board, and proper test vectors that can be executed by a standard Automated Test Equipment (ATE), such as the J750[5].

Due to the substrate being covered with molded plastic, bring up and debug of SiP devices can be challenging. It becomes necessary to use acoustic or x-ray techniques to check component placement, bond wire connections and solder connections of components. Also, it is difficult to perform minor fixes on the SiP substrate, such as blue wiring connections on PCBs, due to the molded plastic. Therefore, any fixes for the SiP substrate require a much longer turn-around time since they must be done either at the SiP assembly house or through a revision of the SiP substrate.

This up-front design and development of a SiP substrate can take a long time and cost a lot of money[6]. This limits the ability to prototype a system with a SiP substrate. Also the functionality of each substrate is fixed, i.e. changes in the system design that do not fit within the current functionality of the SiP, require updates to the SiP substrate Given the pace of technology, a method to more easily prototype and handle requirements changes of an embedded systems is required.

To avoid the fixed nature of SiP devices and improve the ability to prototype using SiP technology, we propose the Universal Connection Matrix (UCM), see Figure 4. The UCM is a matrix of connection pads covering all or a portion of the package substrate. Similar to a solderless breadboard, these pads are generic connection pads. The pads are similar to the surface mount pads on a PCB, i.e. they are just exposed top layer metal surrounded by solder mask. The pads can be any size or configuration but having a regular pattern that corresponds to standard passive components sizes is ideal. Additionally, each pad can have multiple bond wires attached, depending on the manufacturing constraints of the bonder. The size of the pad should support at least two connections, but from experimentation, supporting up to four connections works well given that larger pads are required to support more connections.

On top of these pads, discrete components, such as resistors, capacitors, and packaged devices, can be placed, similar to how surface mount components are mounted to footprint pads on a printed circuit board. Bare die can be attached on top of the pads using standard die attach methods. The discrete components are then electrically connected to the pads either through solder, similar to surface mount components. Bare die are electrically connected to the pads with bond wires from the bond pads of the die to the UCM pads. Once all the components are mounted and electrically connected to the UCM pads, they can then be electrically connected together using bond wires between the UCM pads. The bond wires form an interconnect to complete the desired circuit and allow the components to function together. Similar to a breadboard, the UCM provides the foundation that allows the components mounted on the UCM to be connected together.

To minimize area and cost while still maintaining flexibility, a SiP substrate does not need to be entirely composed of a UCM. There are certain components in an embedded system that are common to many application spaces, for example a microprocessor, memory, and power management. As seen in Figure 5, a SiP substrate can be designed such that common components have a fixed implementation and a portion of the substrate contains a UCM (lower left corner). This heterogenous methodology allows designs to leverage the density of advanced SiP technology while still maintaining the flexibility that the UCM affords.

In a heterogenous SiP substrate, the UCM pads along the edge of the UCM can be connected to the other fixed function circuitry within the SiP, such as processors, memory, or external IO pins. This allows components mounted on the UCM to be connected to the fixed components via bond wires. Similarly, the UCM can have multiple pads that provide power and ground to the components from the SiP substrate.

In the example heterogeneous SiP substrate shown in Figure 5, a 5 volt, a 3.3 volt, and a 1.8 volt power rail are connected to the UCM, which allows a wide range of components to be used on the UCM. Additionally, general purpose IO, analog IO, and digital communication busses, such as I2C, UART and SPI, are routed from the processor in the upper right corner to the UCM. These busses are simultaneously routed to the SiP IO pins so that the connections are not wasted if unused by the UCM. Finally, dedicated SiP IO pins are connected to the UCM so that the UCM components can process external signals.

The generic nature of the UCM allows a single SiP substrate to be used for multiple designs. This enables new customers and markets access to SiP technology. Traditionally, only large volume customers had access to SiP technology due to the high up-front design and development costs. However, the UCM enables low volume customers (i.e. “long tail” customers[7]) access to custom SiP devices by allowing many, low volume products to be manufactured quickly using the same substrate on the same production line by only changing the placed components and bond wire interconnect. Using the same SiP substrate reduces manufacturing cycle time to create a packaged device by more than 75%. The cycle time reduction is primarily due to the fact that substrates do not have to be manufactured for each new device. Instead, new devices can be created by just re-programming the wire bonder and pick-and-place machine. By lowering the cost of creating SiP devices, this opens new integration paths to low volume applications.

Beyond using UCM technology for low volume applications, it can be used extensively where rapid prototyping of small form-factor designs is required. In the same way that an FPGA allows designers to prototype logic circuit designs, the UCM allows designers to prototype SiP enabled embedded system designs. Unfortunately, in the same way that FPGAs consume more silicon area in order to provide design flexibility[8], the UCM consumes more package substrate area than an optimized SiP design. However, just as an FPGA can later be optimized into an ASIC or SoC, the UCM can later be optimized into a custom SiP.

As SiP technology proliferates to more customers, more markets, and more packaged devices, the ability to quickly, easily, and efficiently create differentiated designs becomes paramount. The Universal Connection Matrix and associated design tools to place components and program the wire bonder to connect components, simplify the design process and allows for rapid development of small form factor SiP designs. Simultaneously, this allows low volume customers access to the benefits of SiP technology. As designers once used breadboards to design the next great product idea, in the future, they will use the UCM.

We would like to thank the members of Octavo Systems for their tireless effort and pioneering spirit to enable access to SiP technology, Texas Instruments for their help and support enabling new SiP devices, and specifically Cathy Wicks her for enthusiasm and support.