Solder-Joint Reliability of a Radar Processor for Semi-Autonomous Driving Applications

Every day semiconductor companies, vehicle manufacturers, and other technology providers are bringing semi-autonomous and autonomous driving closer to reality. The future of safe semi-autonomous driving is determined by the reliability of complex technologies, including radar. Today's systems for semi-autonomous driving utilize numerous combinations of camera and radar system designs.

This paper focuses on a micro-processor that will be implemented into corner sensor cocoon radar, in which the sensors are placed at each corner of the vehicle with extra sensors placed on each side mid-body. It processes data received from a SRR, from 0.2 to 30 meters. It is a powerful digital signal processing accelerator, which targets safety applications that require a high Automotive Safety Integrity Level (ASIL-B). This will contribute to applications such as Lane Keeping Assist (LKA), Blind Spot Detection (BSD), and Park Assist for passive safety and 360-degree sensing modules. These applications fall under Level 1 and 2 on the gradation of automated driving. Level 1 encompasses assisted driving, in which assistance systems help the human driver during vehicle operation. Level 2 includes partial automation, in which the human operator must always monitor the system. Generations in the future will cover Levels 3, 4 and 5 towards full automation and operator-free driving [1].

The goal of the study was to determine the baseline solder-joint thermal shock performance of the 0.65 mm pitch, 10 × 10 mm body 141 MAPBGA package. JEDEC drop test, which was not required for qualification, was also collected to recognize potential risk of failures during SMT and assembly. The thermal shock targets were met for the plan of record (POR) package, however further tests were continued on various surface finish and solder ball alloy combinations to fully understand the performance trade-off.

The details of the 141 MAPBGA package are summarized in Table I. The two variables in the study are listed in red. The package is a typical MAPBGA (molded array process-ball grid array) package, which includes the mold cap covering of the entire substrate top surface. However, the die-to-package ratio is high for this package. The die extends past the second to last BGA row on the left and right sides, as shown in Figure 1. Therefore, the SRO (solder resist opening) and solder sphere diameter were designed at about 50% of the BGA pitch to maximize solder-joint reliability, which was verified in previous studies [2]. The package attributes include 0.325mm/0.330mm SRO/Ball diameter for improved substrate routability.

Daisy chain (DC) test vehicle versions of the product package were used in this study to continuously monitor the solder joint integrity during both thermal shock and JEDEC drop testing. The DC components used an electrical pattern on the bottom metal between BGA pads. The overlaid package and PCB DC design is shown in Figure 2.

When the package DC was combined with a matching PCB DC footprint, it created an electrical path that was monitored during SMT and solder-joint reliability. The daisy chain schematic monitored many solder balls through very few data channels. The associated daisy-chain PCB was designed such that there was a total of two nets monitored on each part: perimeter and central nets. Both nets were monitored during thermal shock testing. Only the perimeter net was monitored during JEDEC drop testing, since failures typically occur on corner joints.

The test boards, which were designed with High Tg FR-4 (glass-reinforced epoxy laminate) material, are shown in Figure 3. The surface finish used was OSP and the PCB pad size was a diameter of 0.325mm. The thermal shock PCB was 114 mm by 226 mm and 1.5 mm thick, with eight copper layers. The JEDEC drop PCB was 76 mm by 76 mm and 1.0 mm thick, with ten copper layers. Both board designs followed IPC/JEDEC specifications [3, 4].

Two stencils were used for the thermal shock and JEDEC drop test experimental analysis. Both the stencils utilized anti-adhesion advanced nanocoating for improved volume of paste release and uniformity shape of solder joints during SMT build. The stencil apertures were 0.325mm in diameter (1:1 to the PCB Cu pad), and the stencils were 0.1 mm thick.

The package configurations included two BGA pad surface finishes (Electroplated Ni/Au and OSP) and three solder alloys (SnAg, SAC405, and SAC-Bi). The solder alloy compositions are detailed in Table II. The experimental matrix for this study is depicted in listed in Table III.

The assembled thermal shock PCBs were placed into a dual chamber system for AATS (air-to-air thermal shock). The AATS test evaluated the reliability by repeatedly applying rapidly alternating high and low temperatures to the components. The AATS test cycled between 40°C and +125°C with a dwell time of 30 minutes and ramp time of less than 5 minutes. An elevator system moved the test boards between the two chambers within about 10 seconds. Each AATS cycle was 1-hour long. The temperature requirements for this package was 1500 cycles to first failure. Figure 4 displays a typical temperature profile obtained by placing thermocouples in the solder-joints.

Continuity was continuously monitored using Anatech STD256 event detectors. The event detectors were set to record failures at 300Ω resistance or greater. The Anatech detected events with a minimum detectable event duration of 200 nanoseconds. Each part was monitored in-situ using two separate nets: perimeter and central nets. The cycles to first electrical failure for each component were defined as the first cycle at which the daisy chain resistance increases to 300Ω resistance or greater, followed by nine or more additional events per IPC-9701 [3].

Testing was completed to a minimum of 75% failure. All data was fit to two parameter Weibull distributions using maximum likelihood estimate (MLE). Comparisons were completed based on first failure and characteristic life (Eta).

JEDEC drop testing was completed to simulate conditions beyond recommended end use applications to identify the potential failure modes under a more extreme environment. The drop testing requirements are outlined by the Joint Electronic Device Engineering Council (JEDEC) in the JESD22-B111A specification [4].

Six boards from each cell, for a total of 24 parts per cell, were subjected to JEDEC Condition B of 1500 G drop with a 0.5 ms duration, half-sine pulse. The POR cell consisted of 32 parts (8 boards with 4 parts per board). The PCBs were dropped from an average height of 41 cm to achieve the 1500 G drop. Testing was completed to 75% failure or to 300 drops, whichever occurred first. Using a rectangular rosette strain gauge, PCB strain was characterized during drop testing set-up and found to be up to approximately 1300 μstrain max during the 1500 G drop.

Mechanical cross-sectioning was utilized to characterize the time-zero solder-joints after board mount and for failure analysis (FA) following reliability testing. The samples were prepped with standard potting, sectioning, grinding and polishing methods. Scanning Electron Microscopy (SEM) and Focused Ion Beam (FIB) cross-section images were captured for the study.

Solder paste was printed to boards using a no-clean, halide free, SAC305 ROL0 solder paste with Type IV (28 ± 40 μm diameter) solder powder. Components were placed on boards using FineTech FinePlacer, a dual eyepiece placement machine that aligns parts to the solder-paste print. The fully populated PCB underwent reflow in a ten-heated zone and three-cooling zone convection belt furnace with a peak temperature at 240°C.

Immediately after SMT, time zero cross-sections were completed for all AATS cells (Figure 5). The cells with Ni/Au surface finish had consistent solder joints. However, most of the cells with OSP package surface finish had solder-joints with non-wet regions on the package pad (Figure 6). The non-wet spots did not have intermetallic compound (IMC) on the package pad, indicating that the solder never attached. The non-wet areas appeared in repeating locations, which is indicative of pin marks from substrate-level test. Additionally, SAC-Bi did not appear to wet to the OSP surface properly at both the center and the edge of the joint.

The thermal shock results depended predominately on BGA surface finish material and resulting IMC. Overall the cells with Ni/Au surface finish outperformed the cells with OSP surface finish, as shown in the weibull plot in Figure 7. Each data point corresponds to the first failure on each package, whether on the perimeter or central net.

Additionally, the OSP cells did not meet the target cycles to failure, which was 1500 cycles. All the Ni/Au surface finish cells passed the cycle requirements, including the POR cell of Ni/Au with SnAg sphere alloy. The alloy selection also affected the thermal shock results. Cells with SAC405 sphere alloy had the lowest characteristic lives for both Ni/Au (η = 1968) and OSP (η = 1103) surface finishes, while SAC-Bi had the highest characteristic life values for both Ni/Au (η = 3697) and OSP (η = 2165). Even though SAC-Bi had the highest characteristic life on the Ni/Au cell, the first failure occurred earlier than the other Ni/Au cells. Additionally, the fatigue lifetime of SnAg was better than SAC405 on both Ni/Au and OSP pad finishes. The cross-section analysis on the thermal shock fractures provided further understanding (Figure 8).

All cross-section analysis was performed after 1576 cycles. The first failures on all the Ni/Au and OSP cells occurred near the die edge, which is typical for packages with a high die-to-package ratio. The failures occurred both on the inside and outside edge of the die. The fractures discovered on SnAg and SAC405 cells propagated in the bulk solder near the package side interfacial IMC. In contrast, most of the fractures in the SAC-Bi joints were brittle failures in or along the package side IMC layers. The SAC-Bi joints also had some fracturing in the bulk solder below the IMC, which possibly caused the greater range of cycles to failure and the high characteristic life value.

The JEDEC drop results also depended mostly on BGA surface finish material. However, the results were opposite to the thermal shock results. The cells with OSP surface finish outperformed most of the Ni/Au cells. This is consistent with previous studies [6]. The OSP/SAC405 and OSP/SnAg cells outperformed all the Ni/Au surface finish cells, and the remaining OSP cell, OSP/SAC-Bi, surpassed two of the three Ni/Au surface finish cells. The OSP/SnAg cell did not have any recorded electrical failures. Therefore, the OSP/SnAg data was plotted using estimated Beta and presumed first failure on subsequent drop. The JEDEC drop test results are depicted in the weibull plot in Figure 9. Only the perimeter net DC failures were recorded and plotted.

The analysis of solder alloy drops to failure provided mixed results between the two surface finishes. For Ni/Au surface finishes, SAC-Bi surpassed both SnAg and SAC405 alloys. The SnAg and SAC405 cells had similar low characteristic life values. The opposite occurred for the OSP cells, with the SAC-Bi alloy failing the earliest. The OSP/SAC-Bi also had the lowest characteristic life when compared to the other OSP surface finish cells. Failure analysis was completed on the JEDEC drop fractures to provide further insight (Figure 10).

All cross-section analysis was performed after cells reached greater than 75% failure, except for the unfailed OSP/SnAg cell. Each package that was cross-sectioned had a failure that occurred on a corner joint, which is expected for MAPBGAs during drop test. Most of the fractures discovered were brittle failures in or along the package side IMC layers. The only cell with bulk solder fracturing near the package side was the unfailed OSP/SnAg cell. Additional FIB cross-sections were completed on drop test failures to understand the effect of the surface finishes on the failure mode (Figure 11). In general, the Ni/Au surface finish cells had more brittle fractures than the OSP surface finish cells.

The primary results from this study confirmed that the package pads with Ni/Au surface finish would outperform OSP in thermal shock but not in JEDEC drop testing. Previous investigations by others have shown improved drop results on package OSP pads [6]. The drop test results were hypothesized to be dependent on the IMC compositions formed at the OSP (ex. Cu₆Sn₅) and the Ni/Au (ex. Ni₃Sn₄) interfaces.

The solder-joint reliability results on OSP surface finish cells were potentially affected by the non-wetting areas observed on the time-zero cross-sections, both at the center of the joint and at the edge non-wetting on the OSP/SAC-Bi cell. The ball attach assembly process has since been optimized with decreased non-wetting yield. Therefore, the results with the amended process will be confirmed this year.

The SnAg solder balls had increased cycles to failure when compared to a similar Cu containing alloy. This is also confirmed in previous studies [7, 8, 9]. In this study, SnAg outperformed SAC405. The SAC-Bi alloy offered possible improvements for thermal shock, but the combination of high characteristic life and low beta indicated that multiple failure modes and/or issues in the manufacturing process created unpredictability in the fatigue lifetime.

The results of this study confirmed the solder joint reliability of the POR (Ni/Au surface finish with SnAg solder alloy), which passed 1500 cycles to first failure.

The following conclusions could be drawn from the current study evaluating solder-joint performance of the 0.65 pitch, 10 × 10mm body MAPBGA package:

1. The POR package, which is Ni/Au surface finish with SnAg solder alloy, passes AEC Grade 1 thermal shock requirements of 1500 cycles to first failure with increased 0.325mm/0.330mm SRO/Ball Diameter.

2. Solder-joint reliability can be improved with selection of package pad surface finish material. For this study, Ni/Au surface finish surpassed OSP in thermal shock and OSP surface finish performed better than Ni/Au in JEDEC drop testing.

3. The packages with OSP surface finish were not yet optimized for production, which was determined by the solder non-wet spots issue. Additionally, OSP cells did not meet the temperature cycle requirement. An additional study is in progress with a perfected OSP sphere attach process.

The authors would like to thank Paul Galles for his support in the experimental solder-joint reliability work. Additionally, thank you to Anne Anderson, Alvin Youngblood, and Roy Arldt for their contributions in failure analysis. Also, thank you to Jenny Yang and Y.F Wang, who provided the daisy-chain package.