Thin Core Substrate Large Size FCBGA Stress and Thermal Challenges and Characterization Open Access

Moore's law, to double the number of transistors in an integrated circuit (IC) package by every 18 months or two years, is famous in semiconductor industry. Recently, high speed communication packages require much larger chip sizes and the increased ball/lead counts, in order to meet high input/output (I/O) functionality, requires large size substrate (>50×50 mm²) to content it. High performance flip chip ball grid array (HFCBGA) package is the most popular package type for the high end communication market, which has a metal lid, as heat spreader, on the top of the chip and substrate for warpage control and chip protection [1–4]. With high quality thermal interface material (TIM) between the chip and lid, the thermal dissipation capability is outstanding (>100W), too. However, the good thermal, stress and warpage result comes from professional design and high quality manufacture capabilities. For high thermal performance requirement, the TIM should have high thermal conductivity, thin bond line thickness (BLT), good coverage rate and no delamination, which needs no degradation after reliability test [5–7]. How do these factors impact on junction to case thermal resistance, the widely used index for high power package thermal performance definition, are evaluated in this paper by computational fluid dynamics (CFD) modeling simulation. Generally, the delamination trends to appear at the interface of TIM and chip. Finite element method (FEM) is conducted to evaluate not only the package warpage, but also the TIM/chip interface stress. To control the warpage within criteria and minimize the TIM/chip interface stress to avoid any delamination occur for large size HFCBGA is really a big challenge. As the package size and die size increase, the die to package interaction failure risk increases significantly due to a larger coefficient of thermal expansion (CTE) mismatch region between die and substrate. Meanwhile, design for warpage control and TIM/chip interface stress reduction are conflicting in general. This paper evaluates key factors for mitigating warpage and improved thermal dissipation capability by reducing TIM/chip interface stress. Ring type (stiffener ring only, without lid) design is the other choice for large size HFCBGA. It has the benefit of better thermal performance due to exposed die design, but less warpage control ability and loses die protection capability. Each of lid and ring has its own advantages, which one is better based on demand of die protection. A lid type test vehicle with the size around 65×65 mm² was developed to validate the evaluation. With the proper selected structure and materials, the package can meet all the assembly criteria. The purpose of this study was to develop an assembly technology for high I/O counts, large flip chip package that can meets the requirements of mechanical and thermal properties for packages without compromising reliability and cost.

The test vehicle has a 25×26×0.787 mm³ size 16 nm wafer node chip with 150μm pitch full array bumps, which is flipped and then bonded on a 200 μm core thickness 8-2-8 layers 65×65 mm² substrate; with 1.0 mm ball pitch design, it can content over than 4000 solder balls. The core thickness, 200 μm, is much thinner than traditional ones, ~800 um. Substrate core and prepreg materials were selected as low coefficient of thermal expansion (CTE) materials to control the package warpage/coplanarity. A one piece lid with stiffener ring was the preferred configuration for the flip chip package. Figure 1 shows the structure of this HFCBGA package.

FEM and CFD are used for stress and thermal analysis, respectively. Scanning acoustic tomography (SAT) technique is used for TIM/chip delamination detection. The temperature cycling test (TCT) for reliability confirmation follows the definition of JEDEC standard.

One of the critical phases in manufacturing was the feasibility build with the selected structure and materials. Before mass production, test vehicle (TV) and numerical analysis methods can be used to achieve the purpose of early evaluation. The challenges of larger HFCBGA with thin core besides warpage control and thermal performance required to meet criteria, bump stress performance after reliability test also is a key factor. Therefore, several key design parameters such as substrate core thickness, assembly process and heat spreader design were reviewed in this study.

Warpage control is a crucial factor in semiconductor manufacturing industry to prevent quality problems during the successive assembly process. The excessive warpage may accompany with a lot of issues in such as die/bump crack, solder bump/ball bridging, opening during surface mount technology process, failures during package reliability test. In the traditional assembly process, thicker cores were selected due to larger warpage can be controlled effectively since greater stiffness of thicker cores. However, thin core design is one of the targets of the assembly process. Compared to substrates with thicker core, the advantages of thin core are shrink substrate size, shorter transmission path length for better insertion loss, high speed signal data rate and high quality power delivery requirement. It is well known that packages using thin core substrates have very excessive warpage due to the lower stiffness of thin core substrates, resulted in the difficulty of flip chip bond process, eventually leading to bump cold joint occur. Fortunately, the bump cold joint problem can be greatly improved with magnetic jig. Figure 2 shows the situation of bump bonding with and without magnetic jig.

In the general assembly process, a heat spreader with stiffener ring or a lid is conventionally applied after underfill curing process to reduce the warpage, provide die protection and increase heat dissipation. Generally, it is not easy to control the high warpage using a stiffener or lid for larger package size. It is known that thin core substrates exhibit a severe W-shape when its substrate warpage is controlled by stiffener or lid [8]. In this situation, the thicker lid thickness is accompanied by higher constraints that the heat spreader applies to the package, but the higher failure risk at die corner, including ELK layer of chip or solder bump crack. According to past experience of assembly, lid thickness between 1 mm to 2 mm is often selected for larger package sizes.

Figure 3 shows the stress between die and TIM interface as different core and heat spreader thickness. Form the result, thin core structure has larger die and TIM interface delamination risk due to larger stress. In the other hand, the package with core thickness of 800 μm, the stress between die and TIM interface were not significantly increased as lid thickness from 1 mm to 2 mm. However, when the thickness of the core decreased to 200 μm, the stress between die and TIM interface were significantly increased as lid thickness from 1 mm to 2 mm. From the simulation results, when the thickness of the core decreased to 200 μm, the deformation between die corner and the inner edge of the heat spreader footprint significantly increased, as shown in Figure 4. This local deformation will increase the interface stress between TIM and die, resulting in further poor TIM coverage, as shown in Figure 5. Thus, it's very important, for thin core large size HFCBGA, thin lid is recommended.

In addition, the thermal characteristics analysis of the package is also performed with different TIM coverage and lid thickness. The schematic of the thermal simulation model is shown in Figure 6. In this simulation, the TIM coverage of real package by measurement has been imported as simulation condition. From the simulation results, when the TIM coverage form 94% decreased to 70%, the θ_JC increase about 2.5 times, as shown in Table 1.

For reasons outlined above, even if heat spreader thickness of 2 mm has better warpage control, the poor TIM coverage is still considered to be more important factor of reliability test. Finally, heat spreader thickness of 1 mm is considered a better solution of larger size package with thin core. In respect of substrate design, the dimension of solder resistant opening (SRO) and micro ball (μball) are key factors for the bump stress performance. It is well known that increase SRO and μball size, the risk of bridge were increased. However, excessively small size of SRO and μball may lead to occurrence of cracks on the solder bump. In this study, two different normalized SROs, SRO diameter normalized by bump pitch, have been evaluated. One is 0.47, the other is 0.57. The μball diameter is 5μm larger then SRO diameter. Figure 7(a) shows the cross-section morphology via scanning electron microscope (SEM) of 0.47 normalized SRO after TCT1000 cycles test. The bump crack was found and ultimately led to open/short test fail. In order to solve this problem, larger normalized SRO is selected. From Figure 7(b), more complete morphology was found after TCT1000 cycles test of 0.57 normalized SRO compared to 0.47 normalized SRO; in addition, no bump cracks and bridging were found. From the simulation results, the same phenomenon can be found as shown in Figure 8. From the figure, maximum stress was found in the red box area. Since solder bump stress depends on the bump size, increasing the normalized SRO can effectively increase the bearing area and ultimately reduce the solder bump stress. Therefore, the condition normalized SRO with 0.57 is considered better solution in this device.

Larger HFCBGA with package size 65×65 mm² is qualified along with 200 μm substrate core and 1 mm lid thickness, which has been pass TCT 1500 / uHAST 192 / HTST 1500 reliability test conditions. In this study, the TIM coverage of 1 mm lid thickness above 90%, which has better thermal performance to achieve θ_JC 0.0427 °C/W, and the design of heat spreader play a very important role to improve the warpage resulting from large package size. Finally, the package warpage of this larger size package with thin core after assembled can be controlled within 250 μm and 100 μm at 25°C and 260°C, respectively.