Molding Recipe Study for MUF Solder Crack Improvement Open Access

Flip chip packaging technology has been introduced into many applications over high to low-end products in recent years such as power management IC (PMIC), dynamic random access memory (DRAM), application-specific IC (ASIC), central processing unit (CPU), Graphics processing unit (GPU) because of the advantages of high I/O (input and output) counts, small form factors, thin package profile, excellent electrical and thermal performance. For the coming era, computing performance will play an important role for huge data processing on industries of AI (Artificial intelligence), autonomous vehicles, cryptocurrency, which are mainly established on flip chip copper pillar bumps (FCCuP) technology.

In order to create more I/O bumps on single unit chip area, the bump pitch would be narrowed as well as shrink bump size. To protect the bumps and prevent voids after molding process, two structures would be performed: figure- 1(a) CUF (capillary underfill) and figure- 1(b) MUF (molded underfill). Generally speaking, CUF means to encapsulate underfill first into die gap before molding process; and MUF means to directly fill under and above die by molding compound. In case an unfilled portion is generated, it may cause a failure such as solder flash in the subsequent mounting process. Therefore, excellent filling ability is required for encapsulating materials, and optimization of encapsulating material and molding process of MUF has been studied through several researches [1]–[4].

The benefits of MUF only are increasing process throughput and reducing assembly cost, due to no additional underfill process and material required. A demand for higher density of signal I/O (input and output) counts in smaller die size to acquire enhanced performance and better mobility drives MUF as a major packaging technology [5]. Although MUF structure has such good advantages, it will still suffer some process issues than CUF structure, especially for those critical structure designs. One of the defects that will face is solder crack. The typical defect mode of solder crack is shown as figure- 2, solder was fractured and separated apart by molding compound. The other solder crack mode is shown as figure- 3, there are partial cracks inside the solder, which formed that solder shape is not robust as partial joint. We may not be afraid if our products suffered totally fractured solder crack, because this kind of issue could be sorted by open/short electrical test as an open defect. However, we are considering what if the bump solder is partial joint, then it may pass open/short test at the time-zero (T0) step, but fail in long-term reliability test afterward.

In this article we will focus on the forming mechanism of solder partial crack. Therefore, a hypothesis model would be created, the molding recipe DOE (Design of Experiment) would be planned and verify joint quality by X-section analysis and stress simulation.

To figure out the root cause of partial solder crack, we compared the solder joint shape between CUF and MUF structure on the same test vehicle. The test vehicle is a 12 × 12 mm² FCCSP, with 6 × 5 mm² die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um², respectively. From the solder joint shape comparison shown as figure- 4, we observed that CUF structure has robust solder joint quality without any cracks happened, but MUF structure is much weaker on solder joint shape formation, with solder elongation, necking, or even suffers cracking. This difference is suspected to come from different stresses of different encapsulating materials.

In order to clarify the behavior of encapsulating materials stress, a simplified hypothesis model has been built. We assumed that solder will suffer a tensile force under encapsulation processes, as Fig. 5 shown, which will elongate solder, or even form necking. Although not only underfill dispense but also molding temperature will not melt the solder, however, as found in the literature that solder will easily plastically deform when temperature raises up [6], shown as figure- 6.

To understand the acting force behavior of encapsulating materials for both CUF and MUF structures, a simple formula would be explained:

where F is acting force of encapsulating materials, P is tensile pressure applied underneath die, A is die area, E is young's modulus of encapsulating materials, ɛ is strain of encapsulating materials, L₀ is die gap length, α is CTE of encapsulating materials, here has simplified only CTE2 and E2 contributed since process working temperature is over Tg (glass transition temperature) of encapsulating materials. And ΔT is variance of temperature between peak processing temperature and Tg.

Furthermore, we assume that die gap would be impacted under different encapsulating materials, hence the volume underneath die would be different as well. It could be explained that why CUF structure has no solder elongation phenomenon, but MUF has. Based on the hypothesis, (1) is also can be explained as:

Therefore, we put properties of encapsulating materials as shown in Table 1:

In addition, the acting forces of both encapsulating materials could be estimated as below:

F_UF is acting force of underfill and F_EMC is acting force of mold compound. Assuming ΔV_EMC should be equal to ΔV_UF to approach robust solder joint shape, then F_UF should be equal to F_EMC as well. To let both acting forces close to each other, the result is that molding temperature will be lower than 160°C.

A simulation tool has also been applied to provide evidence of this mechanism, in which a three-dimensional finite element analysis on the panel was performed. The panel is properly constrained to maintain numerical stability. The analysis is carried out using ANSYS v.17. The structure outline regions are shown in figure- 7, where different colors represent different constituents. Three cells of conditions have been added in the simulation: MUF with mold temperature 160°C, 170°C, and 180°C, respectively. The results showed that mold temperature 160°C resulted in lower stress on bump solder (max. 288MPa), compare to 170°C (max. 292MPa) and 180°C (max. 325MPa), which means less strain would be suffered per single solder bump as shown as figure- 8. According to stress-strain curve of solder, the lower the strain on solder, the slighter the plastic deformation will be. This simulation result could explain that lower mold temperature supposed to be benefit on solder elongation shape improvement.

To verify above hypothesis mechanism of solder crack, a DOE (Design of Experiment) matrix has been conducted, shown as Table 2. The factors are mold temperature and mold transfer time, which has been mentioned relates to solder deformation as well [7].

The solder joint quality was judged by cross-section of partial solder crack region. The results as shown in Table 3, showed that both DOE cells still observed solder crack issue, no matter longer mold transfer time or lower mold temperature. However, although all cells suffered solder cracks, the situation was much slighter than original condition. This means that both solutions are toward the right way for solder crack problem improvement. It could also prove our previous hypothesis model from die gap that reduced mold temperature could indeed decrease acting force of molding compound and limit solder from over elongation under molding process.

From experiment results, here are few points that would be addressed:

1. Longer mold transfer time would help on reducing solder crack ratio (40%), compare to original condition (100%).

2. Lower mold temperature would help on reducing solder crack ratio (40%), compare to original condition (100%).

3. Die gap could be reduced by extending mold transfer time or decreasing mold temperature.

In this article, two flip chip structures with different encapsulating materials have been addressed: CUF and MUF. However, solder joint phenomenon showed robust for CUF structure but solder elongating and partial cracking were observed in MUF structure. From cross-section data of two structures, broader die gap was observed in MUF and suspected there should be an acting force of molding compound. A hypothetical solder crack mechanism has been built up and verified through DOE matrix. To improve partial solder crack issue, longer mold transfer time and lower mold temperature showed positive trend.

Although partial solder cracking was observed on all DOE cells, the situation was much slighter than original molding condition. We thought that it might be due to our hypothetical model was established on ideal situation to simplify the root cause finding progress. This means we did not take wafer bump coplanarity and differences between substrate batches into account, especially for such a critical design structure. Minor variance on solder volume or substrate warpage may easily influence die gap and result in solder crack problem. These variances will be considered in further investigation.

The authors would like to take the opportunity to acknowledge the contributions from the great ASE Chung-Li Modeling Lab for stress simulation establishment.