FCCSP IMC Growth under Reliability Stress follow Automotive Criteria Open Access

The automotive integrated circuit (IC) market will outgrow by two even three times of the existing IC market. Market researchers predict that automotive semiconductors will occupy more than 15% of the total semiconductor market by 2025, especially for those analog IC of intelligence vehicle. It is noteworthy that flip chip package becomes the automotive devices solution gradually due to the higher efficiency & complexities of the pin design. More and more design houses are moving toward flip chip or wafer level fan-out package design for automotive infotainment, radar & GPS application. These changes will enable automobiles become reliable and intelligent, so as let the packaging industry prioritize the development of advanced package for next generation of automotive market requirements.

Focusing on the semiconductor industry, more and more devices turn their assembly form from legacy wire bonding to flip chip owing to the higher performance with shorter electrical signal transition path. Also, flip chip package can do more complex design since the transition outset will not be limited at outer ring but full die area. Unlike wire bonding, the flip chip assembly requires the media like pillar or solder bump to link signal between the chips & substrate, hence the interconnect of the microstructural evolution do associate with the effectiveness of reliability.

The Kirkendall Void issue had been raised up [1–3], and lots of experts bring forward the view of why KVs were generated and how to inhibit the existing voids to extend the life time for electronic devices [4–5]. The Kirkendall effect is the atomic movement of a diffusion system with the result of mass flow accompanying by a vacancy flow in the opposite direction. Although the voids exist at the intermetallic layer, the electrical signal may still be able to transit through the voids and passes the functional test. Adding Ni layer is the most common solution to extend the lifetime by blocking the Cu/Sn IMC diffusion since it is more resistant to dissolution into solder joints [6], yet higher resistance will be due to the natural characteristic of Ni layer, even some of the magnetic sensitive devices may have concern for adding these material, hence the lifetime and void formation rate is extremely important for device when do the design from initial stage.

The FCCSP daisy chain test vehicle applied for the current investigation was 6.64mm ×4.98mm die packaged in 9.60mm × 9.60mm with 211 I/O. The daisy chain was designed not only at substrate side, but also designed RDL daisy chain at die side, so as the open/short test could detect the entire signal net. The test vehicle's bonding diagram show in Figure 1.

The test vehicle was prepared following mainstream FCCSP manufacturing technology with four-layer die structure and three-layer ETS substrate, the schematic is show in figure 2. The die design is daisy chain RDL with two polyimide layers and plating bump, then flip chip onto substrate with mass reflow process. After molding, the substrate was singulated to single unit for open/short testing. Table 1 shows the configuration of the package information of the daisy chain test vehicle structure.

Three kinds of bump structure were selected and allocated with two passivation type which are well known as polyimide(PI) and polybenzoxazole(PBO). All the DOE legs are listed in the table 2 below.

Those DOE legs were built up with same mask, except for 1^st layer of passivation, but just revised the mask tone for light transferred. The following daisy chain RDL & UBM process is the same. Hence, the three kinds of electrical connection point & passivation type were comparable for the automotive criteria reliability performance.

The dies after grinding and sawing were assembled into daisy chained ETS test substrate which pad finish is bare Cu pads, and do molding process to protect the whole package. Then, solder paste will be printed at substrate lead side. Before long term reliability testing, all the samples need to do final open short testing to ensure the signal is transmitted. Reliability testing was carried out according to JEDEC specifications and automotive AEC Grade0 as shown in the Table 3 below.

The failure was judged by open short testing, and the failure criterion is zero failure from structure damage. In addition to the monitor of IMC growing morphology, cross section and Scanning Electron Microscopy (SEM) to time zero and every reliability read point were performed.

There are three kinds of bump structure, Cu Pillar with Ni barrier layer, Ni-Free Cu pillar and plated solder bump, the SEM of bumped structure shown in Figure 3. The process flow is all the same but only different in plating sequence.

After bumping process, the three kinds of structure are packaged onto 3-layer substrate with same process flow. The open/short can sort out functional pass units then send for long term reliability testing.

The long term reliability testing result are summarized in table 4. All the DOE legs pass Automotive reliability criteria follow by AEC Q100 Grade0 condition. Each condition had released 77units for testing, and do open/short testing after each read point, and no failure was found when finishing overall condition. Besides, one sample of each read point was picked up for cross section to study the IMC growing morphology.

The IMC growing thickness and analysis are summarized as following. T0 represent the bumped die joint to substrate with one time reflow only, the section for Ni-Free Pillar, Cu Pillar and Solder Bump are shown in Figure 4. The IMC thickness at the interface of pillar Cu and solder, Ni and solder are monitored and recognized due to the KV will be found at the Ni-free pillar condition then compared to with Ni barrier layer cell.

Among all of the DOE conditions, no recognized key factor related to passivation type, the possible reason is that those dies were protected in the molding under-fill, hence the passivation type not impact to the result, so as only the bump structure and read point are comparable.

IMC layer thickness of time zero and final read point 2,000 temperature cycles show at Figure 5. There are two kinds of IMC at the interface of Cu and Pb-free solder of Ni-free Pillar cell, due to the atomic inter-diffusion, Cu₆Sn₅ IMC will be formed at the interface of Cu and solder, then Cu₃Sn layer grows accompany with thermal stress. Ni₃Sn₄ is the IMC formation of the Ni and Pb-free solder, which can be found at the Cu Pillar and Solder bump cell. Ni₃Sn₄ is the first phase to form and to grow into observable thickness in a solid Ni/liquid Sn reaction couple during process.

Precondition and temperature cycling test IMC growing morphology shown in Figure 6. The IMCs are growing steadily with thermal stress. From the chart, it is obviously that the Cu₆Sn₅ and Cu₃Sn growing rate is different from Ni₃Sn₄ IMC with lower growing rate.

If separate the Cu₆Sn₅ and Cu₃Sn IMC thickness for analysis as shows in Figure 7, it can be found that the Cu₆Sn₅ IMC thickness has slightly decrease, and then grows when thermal stress increased. Furthermore, the Cu₃Sn IMC thickness has an increasing rate from time zero to precondition, but cease to grow up when temperature cycling stress join, but the quality concerning Kirkendall Void was found from 200 cycles at Cu₃Sn IMC layer as shows in Figure 8.

The IMC thickness under un-bias HAST test result shows in Figure 9. It is under same phenomenon as temperature cycling stress, Ni₃Sn₄ grows fast accompany with the thermal stress, but Cu₆Sn₅ and Cu₃Sn IMC thickness not showing much difference. The Figure 10 shows Cu₆Sn₅ and Cu₃Sn IMC thickness separately, and Cu₆Sn₅ IMC also convert to Cu₃Sn IMC when the environmental stress participate in, then keep in steady even the testing hours from 96 to 264. Obviously, the 110°C with 85% humidity may not affect to the Cu₆Sn₅ and Cu₃Sn IMC growing morphology in evidence, but the atomic inter-diffusion still exist. The KV issue as Figure 11 under uHAST test is not as serious as temperature cycling test since the added stress is less in temperature and time.

The last test condition need to be discussed is High Temperature Storage which is the most rigorous to IC testing. From the IMC growing thickness analysis in Figure 12, the Cu₆Sn₅ and Cu₃Sn IMC growing faster than Ni₃Sn₄ IMC, at 2000 read point, the total thickness exceed 12um which may be the half of solder stand-off height. The environmental 150°C do affect to the Cu-Sn IMC growing morphology, but not affect to Ni-Sn IMC layer, which remain the same growing rate as previous two conditions.

The Figure 13 explain the Cu₆Sn₅ IMC thickness will be influenced by the continuous heat stress, part of the Cu₆Sn₅ IMC convert to Cu₃Sn IMC, then itself grows up accompany with the stress time and grows up to near average 10um. The Cu₃Sn IMC is also impacted by the heat stress slightly and it becomes thicker over the time. Also, the KV quality is critical for those voids almost connect to each other as Figure 14 shows up. Yet, even under this full of void situation, the open/short testing still give green light for electrical signal transition pass.

When Cu contact with liquid Sn under the temperature range of 112–227°C, the diffusivity of Cu in Sn was much faster, the intermetallic compounds will be formed in the interphase region which can be derived from the binary Cu-Sn phase diagram as Figure 15. The intermetallic Cu₆Sn₅(η) is important due to the large number of tin-lead and lead-free solder joints formed directly to copper. This IMC forms an interfacial layer and can be found in the bulk microstructure solder joints where excessive time and temperature are involved during the soldering process, Cu₃Sn(ɛ) will be converted and grown. The formation of the ɛ phase growth are more complicated [8–10]. However, the Cu₃Sn(ɛ) is the IMC that unwilling to be found since the KV usually located in this layer.

The growth kinetics of the Ni₃Sn₄ phase appeared to be parabolic and diffusion-controlled [11]. Ni₃Sn₄ IMC is the first phase to form and grow into observable thickness in a solid Ni/liquid Sn reaction couple which can be derived from the Ni-Sn binary diagram as shown in Figure 16. After the formation of continuous Ni₃Sn₄, further growth occurs as a result of the diffusion of Sn through the intermetallic layer. The other two equilibrium Ni IMCs, Ni₃Sn₂ and Ni3Sn grow with much slower kinetics and have difficulties in nucleating at the Ni/Sn interface. In both Ni₃Sn₂ and Ni3Sn the main diffusing species during the growth is Ni [12].

1. The FCCSP package can pass through Automotive Reliability Criteria following AEC Q100 Grade 0 condition, with solder bump or cu pillar structure. And the molding under-fill can only protect fragile dies from environmental stress.

2. The Cu₆Sn₅ intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10um at High Temperature Storage 2,000hrs testing, and the second is Cu₃Sn IMC.

3. Cu₆Sn₅ IMC will convert to Cu₃Sn IMC at initial stage, then Kirkendall void will be found at the interface of Cu & Cu₃Sn IMC, which has quality concerning issue if the voids density grows up.

4. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni₃Sn₄ IMC, and the thickness has little relationship to the environmental stress since no IMC thickness variation between TCT, uHAST and HTSL stress test.

5. The more the Sn exists, the thicker Ni₃Sn₄ IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell.

The authors would like to thank ASE Group, Chung-Li QA lab team (Steven Shih) for supporting the reliability testing, and R&D lab team (Dr. Fresh Tseng) for cross-section and SEM measurement.