The Effect of Nickel Oxidation Formed in the Interface of ENEPIG Structure for Flip Chip Technology Open Access

In microelectronic package, the smaller solder ball is used in chip and substrate joint. This may have an adverse influence for the reliability in electronic products. Moreover, the European “Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment” (RoHS) was effective. Many new Pb-free solder was developed to compete with SnPb solder on soldering performance as surface finish, flux wettability and reliability performance improvement. One of the most popular Pb-free solder is Sn-Ag-Cu which may replace of SnPb solder. Due to most property of Sn-Ag-Cu is better than others. [1–4]. Au/Ni (ENIG) is one of key technology of substrate market. but there is “black pad” issue for ENIG substrate. Another electroless Ni(P) / electroless Pd(P) / immersion Au (ENEPIG) with wide application was developed, too. [5–7]. For the ENEPIG, the Ni layer is a diffusion barrier layer to avoid the reaction between the Cu and solder, which induced by Cu diffusion. The Pd(P) layer was as a diffusion corrosion barrier, which can be prevent a “black pads” formed location in the Ni(P) surface from the galvanic hyper-corrosion induced by the immersion Au plating. The Au layer has the function for oxidation resistance and wettability between the solder and pad [8–10]. Thus, the mechanical strength of solder joint is an important topic for the major reliability in electronic assembly technology. In Tseng et al. study [11], the Pd thickness is reveal an important role of the crack induce by needle-like (Cu, Ni, Pd)₆Sn₅ formation during the reaction of Pb-free solder and ENEPIG substrate. In Ho et al. study [12], the lower shear force reason was induced by the Ni(P) corrosion within ENEPIG interface layer. In our study, we found intermetallic compound (IMC) cracks issue for ENEPIG interposer product, and we analyzed the failure samples, for ENEPIG processes verified to find out the IMC crack root cause.

In this study, the ENEPIG layer was deposited on 120 μP opening Cu pad of a chip carrier substrate. The thickness of ENEPIG layers were 5 to 8 μP (Ni(P)), 0.1 to 0.2μP (Pd(P)) and 0.05 to 0.1 μP (Au), respectively (in Fig. 1). The phosphorus ratio of Ni and Pd layers were 6 to 8 wt% and 2 to 5 wt%, respectively. The deposition of Ni(P)/Pd(P)/Au layers used the electroless plating technology [13]. The compositions of solder paste were 96.5 wt.% Sn-3 wt.% Ag-0.5 wt.% Cu (Sn3Ag0.5Cu), and solder size after reflow is 150 μm around. Why we research this experimental parameter? Because, we are review the ENEPIG process no any production monitor data abnormal can be found (e.g. temperature, concentration, dipping time, circulation, overflow, bath life and all in control limit), thus, which are online observation finding the exposure time above electroless Ni bath. Therefore, the schematic diagram of ENEPIG process for the exposure time on the top of Ni bath (in Fig. 2), thus, the exposure time for samples were 1s, 6s and 20s. All of the samples were cold mounted and general cross-section procedure to observe the joint interface microstructures. We found IMC cracks issue for ENEPIG Interposer product by using Scanning Electron Microscope (SEM). We analyzed the failure samples, the ENEPIG processes and verified with modified the ENEPIG processes to find out the IMC crack root cause. These samples of interposer pad structure was made by production ENEPIG process, and the sample exposure time on top of Ni bath will affect the nickel compounds formed, moreover, the observation and analysis of these samples by using SEM, Focused Ion Beam (Helios G4 UC, FIB), Transmission Electron Microscope (TEM) and Energy-Dispersive X-ray Spectroscopy (EDX), thus, the EDS to do the line scan and point analysis. These samples with solder were further reflowing by difference exposure time for interfacial reaction observation to clarify the nickel compounds influence on crack issue. Then, these samples will through the soldering reaction between solder paste and ENEPIG layers substrate was performed under atmosphere controlled furnace, and then, which observed the adhesion strength between ENEPIG and solder were observed by hot bump pull (HBP) test (Nordson Dage 4000 Plus).

In Fig. 3 (a) showed SEM image results, the solder crack sample appear location in ENEPIG substrate side. In Fig. 3 (b) showed SEM and EDS mapping at the solder crack location, thus, which observed the cracks separate at Ni / solder interface, moreover, the interface of Ni/Sn no obvious IMC formation. Further, in Fig. 4 (a) and (b) showed TEM image and line-scan analysis results, the crack appear location in Ni layer surface, which was the thin Ni-P IMC layer formed and then crack, thus, also no observed soldering reaction problem between ENEPIG and solder, then, line-scan indicated the cracks appear location in Ni(P)/solder interface.

We are review the ENEPIG process no any production monitor data abnormal can be found (e.g. temperature, concentration, dipping time, circulation, overflow, bath life and all in control limit), thus, which are online observation finding the exposure time on top of Ni bath. We did the Ni(P)/Pd(P)/Au layer process analysis, which suspected the Ni compounds formation between Ni bath and rinse. Thus, the samples exposure time on top of Ni bath is important factor. Therefore, the different exposure time on top of Ni bath was arranged for ENEPIG interface observation. Further, in Fig. 5 (a), (b) and (c) showed FIB image results for the exposure time were 1s, 6s and 20s. The black point was found between Ni(P) and Pd(P) interface for the exposure time were 6s (some black point) and 20s (more black point).

Due to we found the black point existed in Ni(P)/Pd(P) interface, thus, we want to confirm the attributes of the black point, which are further analysis the black pinot location by TEM. In Fig. 6 (a), (b) and (c) showed TEM image results, in Fig. 6 (a) the exposure time was 1s, which no found the void formed at Ni(P)/Pd(P) interface. In Fig 6 (b) and (c), we found the voids existed in the interface of Ni(P)/Pd(P) layer for the exposure time were 6s and 20s, thus, we suspect Au penetration path is along Pd(P) grain boundary, therefore, the exposure time were 6s and 20s, which obviously Au penetration path is along grain boundary and the voids were found in Ni(P)/Pd(P) interface.

According to FIB and TEM images observed analysis results, which proved the black point = voids existed in Ni(P)/Pd(P) interface, further, we want to confirm the voids attributes in Ni(P)/Pd(P) interface by TEM line-scan. In Fig. 7 (a), (b) and (c) showed TEM line-scan results, the interface of Ni(P)/Pd(P) layer no found the strong oxygen signal for exposure time were 1s, 6s and 20s. Further, we want to confirm the oxygen signal whether exist in Ni(P)/Pd(P) interface by TEM mapping. In Fig. 8 (a), (b) and (c) showed TEM mapping results, in Fig. 8 (a) which no obviously Au penetration signal for exposure time was 1s, thus, in Fig 8 (b) which obviously Au penetration path signal in Pd boundary for exposure time was 6s, then, in Fig. 8 (c) which found the wider Au penetration path was detected in Pd boundary and the voids were observed in the Pd(P)/Ni(P) interface for exposure time was 20s. These experimental results demonstrate the exposure time will affect the voids formation. Therefore, as the exposure time is too long (the exposure time is 20s), more bigger voids was formed in Ni(P)/Pd(P) interface.

In addition, we want to confirm these materials migration path attributes in Ni(P)/Pd(P)/Au interface by TEM-EDX point. therefore, in Fig. 9 (a) showed the TEM image and EDX point (in Table 1) analysis, which found the Ni and Au signals existed at EDX-point 4 on Pd(P) layer for exposure time was 6s, moreover, in Fig 9 (b) showed TEM image and EDX point (in Table 2) analysis, which found the same situation for the exposure time was 20s, then, EDX-point 1 to 4 have the Ni signals existed, then, EDX-point 1 to 3 have the Au signal existed, therefore, which proof the nickel migrated into Pd(P) layer and Pd(P)/Au layer, moreover, we observed the apparent signal for Au penetration path between Pd boundary, then, the grain boundaries of Pd(P) layer have micro voids and slot existed, thus, the micro voids formed location in Ni(P)/Pd(P) interface during Au deposition process, the galvanic hyper-corrosion induced by the immersion Au plating, then, the Au plating liquid penetrate into Ni(P)/Pd(P) interface along voids and slot for Pd(P) layer and induced chemical reaction and replacement [10], the nickel have migrated into Pd(P) layer and Pd(P)/Au layer. These micro voids can be fatal defect for solder crack of the solder joints. Considering, in Fig. 9 (a), (b) and Table 1, 2 showed the nickel migrated path signals and Au penetration path signals in Pd boundary were existed.

Further, we want to confirm the joint between solder and ENEPIG substrate by HBP. In Fig. 10 (a) showed the schematic diagram for solder and ENEPIG substrate joint, then, Fig. 10 (b) showed the image for HBP pin tip and solder connection. In Fig. 11 (a) and (b) showed HBP test results, the adhesion strengths of solder joints for exposure time were 1s, 6s and 20s. The HBP speed is 0.1 mm/s. In Fig. 11 (a) showed the different reflow times (1, 5 and 6 times) vs. the different exposure time (1s, 6s and 20s) compare, as exposure time together with reflow times increased, and the solder joints strength were decreased. In Fig. 11 (b) showed the different long storage time (10hrs, 100hrs and 1000hrs) at 150°C vs. the different exposure time (1s, 6s and 20s) compare, as storage time together with storage time increased, and the solder joint strength were decreased. In addition, the short exposure time (1s) had the best HBP strength than the longer exposure time (6s and 20s). Therefore, the formation of voids affect the adhesion strengths for solder joints in Ni(P)/Pd(P) interface.

Considering, the experimental analysis and results indicated the voids in Ni(P)/Pd(P) interface will affect solder cracks formed. According to Arulraj et al. study [14], we derived the chemical reaction formula (1) for the surface of ENEPIG substrate (on Ni layer surface) have some sulphuric acid and water residue, which are exposure on top of Ni bath, then, them suffer interaction at temperature and air:

Another, according to Wu et al. study [15], we derived the chemical reaction formula (2) for the micro voids formed in Ni(P)/Pd(P) interface during Au deposition process, the galvanic hyper-corrosion induced by the immersion Au plating, then, the Au plating liquid penetrate into Ni(P)/Pd(P) interface along voids and slot for Pd(P) layer, and then induced chemical reaction and replacement, moreover, which can dissolved and migrations for NiOH by CN²⁻:

Therefore, according to the chemical reaction formula (1) and (2), which suspected the compound of NiOH (Ni oxidation) was existed in Ni(P)/Pd(P) interface, such reveal the mechanism of IMC crack failure mode (in Fig. 12): 1. Too longer exposure time on top of Ni bath, which will induced NiOH (nickel oxidation) formation on Ni(P) layer surface; 2. The Au chemical penetrates along Pd boundary and NiOH (nickel oxidation) was dissolved into Au chemical by CN²⁻; 3. The void formed location between Ni(P) layer and Pd(P) layer; 4. The crack propagation was along the void in Ni(P)/Pd(P) interface by stress. (e.g. substrate warpage).

IMC cracks were induced by the nickel oxidation formation in the interface of the ENEPIG layer. By controlling the exposure time to the nickel batch, nickel oxidation can be avoided which reduces the risk of the IMC crack failure mode. The root cause of the IMC cracks may be attributed to the following failure modes: 1. The existence of nickel oxidation; 2. The nickel oxidation was dissolved and migrated into Au chemical by CN²⁻; 3. The voids formed location between Ni(P) layer and Pd(P) layer; 4. The crack propagation was along the voids in Ni(P)/Pd(P) interface by stress.

This work is supported by Advanced Semiconductor Engineering, Inc.