A Systematic Approach to the Reliability Characterization of System in Package (SiP) Open Access

This paper describes a methodology to systematically characterize critical factors that contribute to reliability of ball grid array (BGA) SiPs. Instead of using an application specific SiP package, authors used a development vehicle to demonstrate this approach. First, Shadow-Moiré technique was used for high-temperature warpage measurements of both the individual components as well as a fully assembled SiP. This information was used to ensure a robust SiP assembly process and yields during reflow of the SiP onto a higher-level PCB. Next, a calibrated digital image correlation (DIC) system was used to measure the global Coefficient of Thermal Expansion (CTE). DIC analysis was used to characterize individual packaged BGA components, the SiP substrate, a fully assembled SiP and finally the motherboard to which the SiP would attach. The data collection from Shadow Moire and DIC were instrumental in providing a physical understanding of the thermo-mechanical dynamics of each component and their mismatches when combined into a single SiP solution. This data collection helped to identify potential high stress locations in the design and ultimately identify failure/concern areas.

SiP design requires identification of a solution within a tight window of manufacturing, electrical, cost, timeline, and SiP assembly quality and reliability constraints. To add to the challenge, it can often take several months to characterize the impact of decisions made early in the design phase on the quality/reliability attributes using prototypes. To avoid this delay during the development cycle, a systematic approach was undertaken to evaluate the impact of design and material selection on key thermo-mechanical risk factors using Finite Element (FE) models. Global finite element models were used to capture SiP warpage with detailed BGA level models used to predict solder-joint interconnect reliability. To vet this approach, an early methodology flow and correlation between the collected test and simulation data was undertaken and described within this work. Although the work is preliminary, this systematic approach of characterization, followed by reliability testing and FEA guidance is the most suitable approach to tackle array of complexity looming from SiP packages or system solutions.

The SiP development vehicle used to explore this methodology in this work is illustrated in Fig. 1. Layout shown below is not to scale. The SiP substrate was a multilayer organic laminate with high density interconnects. A mix of FCCSP and FCBGA components with SAC alloy solder balls were attached to the SiP substrate with a variety of pitches >0.4mm using a conventional reflow process. While Components B and C were unique part IDs in the design, Component D was a repeat of Component A.

Out-of-plane warpage behavior was collected on samples using Shadow-Moire analysis. The tool includes an integrated oven and heat is generated by IR lamps positioned below the sample. The tool was set up to analyze a single unit as a region of interest (ROI). The grating frequency was set at 100 lines per inch. Lateral and vertical resolution set at 4mm/pixel and 2.54 microns respectively. Shadow-Moire is a well understood technique which is frequently used for high temperature warpage analysis [1]. Yet several challenges were presented for larger form factor SiP devices. Some learnings and the results are discussed below. While Shadow-Moiré is a common analysis technique for stand-alone IC packages, applying the same principles to a larger and more complex SiP can present some challenges.

Thermal gradients are inherent due to single sided heating, there was concern of lateral gradients resulting from different thermal mass of the components attached to the SiP. Non-uniform heating can induce different warpage behavior that does not represent a true production process. To achieve the best thermal uniformity, the tool was set up by placing the device as close to the heaters as possible while still maintaining an appropriate working distance from the grating. The device was measured in ‘deadbug’ orientation, with the BGA side up and viewed by the camera. Three thermocouples were attached to determine thermal uniformity. The process control thermocouple was placed on the BGA side, and two additional thermocouples monitored the uniformity both through the thickness as well as laterally.

A peak reflow temperature of 245°C would be used in production, and an appropriate profile was developed in the shadow-moiré tool. Fig. 2. shows an example diagram of the setup, while Fig. 3. shows the measured thermal profile. Post-analysis shows that less than a 10°C differential existed across the sample, minimizing effects of thermal gradients. This result confirmed that proper setup and profiling could achieve accurate results even on a larger form factor, complex SiP device. Thermocouple locations shown by numbered stars correlate to measured thermal profile in next image.

The next hurdle was proper sample preparation. Typically, stand-alone BGA packages are measured on the ball side (dead-bug) and solder balls are removed so that the tool can image directly on the substrate surface. Initial analysis on SiP devices suggested that the solder balls could remain because the pitch was so coarse that sufficient data from the substrate could be collected. However, the periodic nature of the ball pitch ultimately created an optical interference pattern, resulting in what is referred to as “banding” of the surface. Once solder balls were removed, the banding issue was resolved. Fig. 4. shows the improvement by removing solder balls.

Once the setup was determined to be robust, the warpage analysis was straight forward. The only particular noteworthy result from the analysis was the local variation in surface curvature as a function of front-side components. Regardless of configuration tested, the largest curvature was found directly opposite the stiffest component. Fig. 5. shows a reference example of one tested configuration with the approximate location of the largest front-side component overlaid. Regardless of front-side layout, all configurations analyzed had acceptable room-temperature and high-temperature warpage that would translate into a robust manufacturing process. Warpage of individual components were measured but values were very low in the range of 10–50 um range which did not pose any significant challenge for SMT or assembly.

Digital image correlation (DIC) was a secondary metrology used for thermomechanical characterization of the SiP devices [2]. While this technique also can measure out-of-plane deformation, the primary benefit and focus of this analysis was to measure in-plane deformation. Captured under thermal loads, the global device thermal strain and ultimately the effective Coefficient of Thermal Expansion (CTE) can be calculated for finite element model correlation. Instead of simulating a solder reflow process, the thermal profile simulated a board level thermal cycle, so peak temperatures of less than 200°C were targeted for characterizing the SiP and individual components for stress analysis.

Sample preparation is key to ensuring high lateral resolution. A speckle pattern must be applied to the surface being analyzed. This was done by first coating the surface in white paint, followed by very light, discontinuous coat of black paint to create a speckled surface with non-uniform dot size and distribution. Fig. 6. shows an example of the component surface after sample preparation. The 2-camera system of the DIC tool tracks the relative movement of the speckles and generates a deformation map in both axes, relative to the un-deformed state. The effective CTE is then calculated by dividing the slope of an extracted line plot by the temperature differential. An example of this process is shown in Fig. 7. Sample flow to calculate CTE for horizontal displacement function is shows. Vertical displacement function follows the same flow, but the extracted line runs vertical through the sample. Learnings and observations are discussed below.

All components soldered to the SiP, along with the SiP itself were analyzed for CTE in the DIC tool. In addition, both the bare SiP substrate and the final PCB motherboard to which the SiP would solder were also analyzed. The data collected from this thorough review helps enable a more robust Finite Element (FE) model, but also allows for quick relative analysis for reliability risk assessment. Fig. 8. shows the summarized CTE results, normalized to the SiP substrate.

Major take-aways are listed below:

• The bare SiP substrate and the full assembled SiP have virtually identical CTE values, meaning that the components soldered to the SiP do not significantly affect the lateral expansion rate at the SiP BGA side.

• The individual component CTE values are all less than the SiP substrate, indicating a potential solder joint reliability risk due to stresses incurred from CTE mismatch. Component A or D would be the most likely to fail based on pure CTE mismatch.

• The CTE of the SiP assembly closely matches the CTE of the motherboard, so the risk of solder joint thermal fatigue failure is deemed low for this interconnect.

Reliability testing of a similar SiP device was performed in a dual chamber thermal-cycle chamber using a profile of −40°C to 85°C. The cycling frequency was 1 cycle per hour. The measured profile is shown in Fig. 9. Samples were pulled from testing at selected intervals throughout the total test duration and typical failure analysis techniques were used to assess solder joint damage. Dye and Pry analysis was found to be the best methodology for assessing solder joint cracking of the various component attached to the module. Crack areas could be quickly determined and crack growth rates calculated over the period of test.

To understand the thermomechanical reliability, assembled SiP devices were subjected to extended thermal cycle testing as described above. At select intervals, devices were removed and analyzed for solder fatigue through dye and pry analysis and selective cross-sectional microscopy. A calibrated guide was used to subjectively determine crack lengths from the dye and pry analysis, as shown in Fig. 10. For a semi-quantitative analysis, only solder joint cracks greater than 50% of the joint were counted for each component type and cycle count. The plot in Fig. 11. shows the cumulative analysis, clearly indicating that Component A has the highest fail rate. In fact, component A exhibited solder joint cracks of 100% as early as 50% of the way through the total test duration. Components B and C exhibited no cracks of 50% or greater even up to 83% of the total test duration. This result correlates with the CTE mismatch observation from the DIC analysis. Finally, the fully assembled SiP mounted to the motherboard was analyzed at the total test duration. There was no evidence of failed solder joints between the SiP and the PCB, further confirming the CTE analysis, which showed the SIP device and motherboard had very comparable CTE values.

Finally, if we compare CTE data from DIC measurements and reliability test results from thermal cycle (TC), the highest CTE mismatch was expected between Component A and SiP substrate. Thus, the TC results clearly showed higher fail rate (or) higher solder joint degradation for the solder joint interconnects from Component-A which is mounted on to the SiP substrate. The failure here is driven by shear stress on to the solder joints. All other Components and module level solder interconnect had very high reliability performance. Now, in the next section we can see how FEA modeling can help aid in early design and development of SiP. Authors will also show example test cases from FEA on how combining baseline information from material characterization and reliability testing can be utilized as groundwork for reliable FEA feedback loop for product development.

A full 3D Finite Element (FE) model was used for both Warpage and Board Level Reliability (BLR) Temperature Cycle (TC) assessment. ANSYS [3] was used as a FEA tool for both the analysis. Element type SOLID185 was chosen for both the models and solder is modeled with creep behavior. Most of the modeling attributes are chosen based on the best guidelines from both internal practice and published papers [4, 5]. SiP layout as shown in Section I was modeled and data from material characterization such as composite CTE from DIC as shown in Section II was used as one of the key inputs for modeling. Also, authors used relatively less complex 3D solid FEA model for warpage and detailed modeling approach for BLR assessment. Details are discussed under each section below.

Package coplanarity and high temperature warpage are the key metrics to control at the end-of-line assembled product. Thus, a FEA based feedback loop is needed at the early stage of development work to fine-tune complex SiP package. This approach help analyze design choices such as component placement, SiP substrate selection, substrate thickness, etc. Warpage modeling is very challenging in general to predict the exact behavior from assembly manufacturing process. Key component that can be captured with ease is relative thermo-mechanical mismatch coming from various components, substrate and their interactions. Thus, a simplified warpage model was used with composite single layer SiP substrate. Composite CTE values from Section II was used for quick prediction and guidance. Fig. 12. shows contour plot of warpage at room temperature (RT) and high temperature (HT). Warpage shape at 25°C (RT) was Crying shape (+ve) and warpage shape at 200°C (HT) was Smiling shape (−ve) assuming all components facing up. As shown below, both RT and HT warpage were driven by location of largest component C. Although Component A has the highest CTE mismatch with SiP substrate, the form-factor and stiffness of package C is much larger, and it enhances the mismatch. For this test vehicle, HT warpage value was well within specification and less of a concern for SMT. Thus, focus was more on package coplanarity. As shown, FEA can be used here to study such critical factors and their interactions. E.g. Component placement effect during SiP development phase.

To demonstrate another case study with goal to reduce package coplanarity, simulation DOE on SiP substrate was conducted. Authors compared two factors and two values for each. Two factors are substrate thickness, 1.0 and 1.4 mm and substrate materials A with CTE of 1.0X and material B with CTE of 0.9X (relative to Material A). Rest of the component geometry and form-factors are all kept constant. Predicted warpage results are as shown in Fig. 13.

As shown above, CTE drop in SiP substrate by 10% resulted in RT warpage improvement of approx. 10–15% here. Also, thicker SiP substrate helped reduce warpage by approx. 20–25% depending on the material used. Another point to note here is that, results from substrate thickness improvement was reflected on recent empirical data showing ~20% warpage improvement with thicker substrate B. Thus, authors recommend using such early FEA tools can help reduce significant cost and time during the initial phase of the SiP development.

In this section, Solder Joint Reliability (SJR) of the critical BGAs are modeled for the development vehicle discussed in Section II. This includes BGAs that connects Component A, B, C and D with the SiP substrate (1^st level interconnect) and the BGAs that connect SiP substrate with the final PCB motherboard (2^nd level interconnect). Solder joint model for both the interconnects are as shown in Fig. 14. The key challenge for this FEA model was to develop a parametric model that truly spans and captures all the components, SiP substrate and the PCB board at the same time in the same analysis. This is critical to study and understand the interaction of solder joint stresses. A multi-level global and local models were used for each component and combined using Constraints Equations in ANSYS across the Z or thickness interfaces. Typically modeling all interconnects in SiP for reliability modeling can be a daunting task. However, relatively less complex process can be achieved if chose to model each package component as one entity by assigning composite CTE. This approach can help fast forward the model development time and quickly evaluate weak BGA interconnects in the SiP package. As expected less complex model would support quick but crude assessment. While detailed assessment is complex but more accurate. Authors recommend detailed approach as discussed here. Either of the approach needs to be calibrated using test data for real time product development. Also, Strain Energy Density (SED) is used here as a relative stress metric for comparing various joints in the SiP package.

Finally, simulation was run for a baseline case and SED was calculated for all the critical joints from Component A–D and for the SiP BGAs. Results are as shown in Fig. 15. Higher SED number refers to higher stress accumulated by the joints i.e. rapid failure due to solder joint crack. Now, if we compare FEA results with test data shown in Fig. 11., there is clear correlation that BGAs of Component A which is connected to the SiP substrate is the weakest interconnect. FEA simulation model confirms empirical data showing highest stress or SED is from Component-A BGAs. Thus, FEA can be used in the early product development phase to flush out various design attributes or choices. FEA can also be used as full feed-back loop as more test data strengthens the confidence of design space that can be assessed using simulations.

In this paper, authors discussed a systematic approach for characterizing various components used in SiP modules and further extend that approach to assess reliability aspects of SiP using both testing and FEA modeling. While detailed analysis and findings are discussed under each section, identified below key takeaways from this study.

• Basic test characterization using Digital Image Correlation (DIC) to estimate Composite CTE of a component or material stack can be used as leading indicator for identifying problem areas for SiP solutions.

• CTE mismatch from DIC measurements shows the weakest link in the whole SiP module when mounted to PCB. Thermal Cycle (TC) reliability testing clearly showed early failures in BGAs connecting Component-A (or D) with SiP substrate.

• A methodology flow was established by taking the material characterization inputs such as Composite CTE and warpage to calibrate the early model and further assess Solder Joint Reliability for all BGAs at PCB board level. Simulation results also proved that the weakest BGA interconnect was from Component-A (or D). Such information is very critical during product development phase to address the weakest link and further improve overall reliability.

• While, a calibrated FEA model can be used for tuning the entire SiP system, a case study was demonstrated here using simulation DOE of substrate thickness and materials. However, even if the FEA model is not fully calibrated across various design attributes, an early guidance of each factors will help fine-tine actual process DOEs. Thus, authors recommend this early systematic approach in combining material characterization with FEA for initial guidance. With more test data and calibration, such FEA models can be extended for actual life predictions.

SiP packages or modules have always been complex and its getting more complex in current ecosystem. Thus, a systematic approach as shown in this paper using basic characterization, reliability testing followed by FEA feedback loop can provide early understanding of weakest link in the SiP development from thermo-mechanical perspective. This will set a stage for developing cost effective and reliable SiP package solutions.

Authors would like to thank Qualcomm Technologies, Inc. management for its support on this paper. Ahmer Syed, Ryan Lane, Mark Schwarz and Milind Shah of Qualcomm Technologies, Inc. Packaging for their valuable feedback and continuous support. And special thanks to Donato Esteban from the Qualcomm Technologies packaging lab for significant contributions in both metrology and failure analysis.