System ElectroThermal Co-Design of a Zero-Drift Current-Shunt Monitor with Precision Integrated Shunt Resistor Open Access

Precision current sensing resistor has many applications areas, among which are Telcom (hot swap controllers), computers, battery management (fuel gauge sensing), and Test Equipment (current monitoring). Currently, the solution for shunt current sensing is the combination of the external standalone discrete shunt with a controller which allows at best accuracy of 2%. Additionally the accuracy is compromised by several factors, among which are DC losses in the package/PCB trace and inadequate shunt material type with high temperature coefficient of resistance [1–3]. To overcome these challenges, integrated schemes have been developed.

A typical signal chain, in an integrated current sensing solution, for monitoring a current signal involves integrating the analog front-end (AFE), an analog to digital converter (ADC), and a system controller as shown in Figure 1[4]. The higher level of integration leads to higher performance and reduced system cost. Using a low-Ohmic shunt resistor helps to reduce the current sensing power dissipation. Since the voltage drop in low-Ohmic resistors is correspondingly small, error voltages not produced by a current flow can impact the performance. For this reason, it is essential that the product developer and layout designer understand the causes and minimize their influence through careful package and PCB layout/physical designs. The effective resistance value is dependent on many parameters such as temperature, time, voltage, frequency, among others. Parasitic resistances in series with the shunt resistor can cause additional measurement errors as current flows through the resistance to create the shunt voltage. These parameters impact system performance.

In Section II a description of the device is provided. Section III details the electrothermal (ET) co-design methodology employed to assess parametric impact on device performance for HVM through DOE analyses. Section IV outlines the system co-design approaches. Measurement to simulation correlation findings and observations are presented in Section V.

The device features a 2-mΩ, precision, current-sensing resistor and a 36-V common-mode, zero-drift topology, precision, current-sensing amplifier integrated into a single TSSOP package. High precision measurements are enabled through the matching of the shunt resistor value and the current-sensing amplifier gain providing a highly accurate, system-calibrated solution (Figure 2). For a detailed description of the device see reference [5].

The low-drift, current-sensing resistor allows for high precision measurements over the entire specified temperature range of −40°C to 125°C. The integrated current-sensing resistor ensures measurement stability over temperature as well as improving layout and board constraint difficulties common in high precision measurements. The onboard current-sensing resistor is designed as a 4-wire (or Kelvin) connected resistor that enables accurate measurements through a force-sense connection. Connecting the amplifier inputs pins (VIN− and VIN+) to the sense pins of the shunt resistor (SH− and SH+) mitigates some of the parasitic impedances commonly found in typical very-low sensing-resistor level measurements. Under the conditions of no air flow, a maximum ambient temperature of 85°C,and 1-oz. copper input power planes, the device can accommodate continuous current levels up to 15 A.

The device is packaged in a 16-pin TSSOP package of 5.0×4.4 ×1.0mm in size. The low-Ohmic shunt resistor is a Cu alloy with a very low temperature coefficient of resistance. Current is sensed by measuring the voltage drop over the two sense pins (Fig. 2). The current consumption of the silicon is relatively low, leaving the total package resistance carrying the high load current as the primary contributor to the total power dissipation of the package. Maintaining constant resistance value over the PVT (process, voltage, temperature) conditions is critical to achieving high performance. Methodology for accurate resistance extraction and electrothermal analysis is discussed in the next section.

The system co-design modeling methodology employed to characterize the electro-thermal solution space of the shunt resistor, under PVT and manufacturing conditions, is thoroughly detailed in reference [6]. To summarize, the methodology involved the fundamental solutions of governing equations that coupled electrical and/to thermal dependencies. Electromagnetic solver is used to solve the conduction current and computational fluid dynamics (CFD) solver to solve the thermal (see equations below).

Current is a function of device temperature, which in turn, is determined by the dissipated power. Therefore the determination of device current (i.e. power) and a temperature represents a coupled electro-thermal problem. The co-analysis methodology contains two functional modules: 1) physical field solvers and 2) equivalent circuit/network solver [7–8]. The field solvers resolves the electrical and thermal field variables by the conventional 3D finite-element method, while the network solver can achieve accurate and efficient results by connecting the equivalent electrical, thermal and flow circuits that are extracted from the system through advanced numerical schemes including Finite-Element Analysis (FEA) and Computational Fluid Dynamics (CFD). The integrated equivalent network can then be solved by a generic circuit solver for the transient and steady-state responses due to electrical and thermal interaction, and the heat dissipation to the surrounding fluid is also taken into account [9].

In the physical conventional field solvers the governing equations are solved iteratively based on the physics of electrical and thermal formulations respectively. The electrical conductivity tensor is a function of temperature. For electrical and thermal solutions, Ohm's Law and the Thermal transport equations are solved respectively. To effectively carry out electro-thermal co-simulation, the boundary conditions to be imposed to the problem are critical to achieve results that are coherent with physics and fit for realistic applications. Electrical boundary conditions should include the driving forces of electrical potential and the current requirements on the package and die to perform the functions as designed. These electrical boundary conditions are applied at specific ports or terminals in the geometrical model. Thermal boundary conditions are basically characterized as heat-in and heat-out mechanisms associated with the system. In general, the heat-in mechanism is the power input (or consumption) through the chip, and the heat-out mechanisms account for heat dissipation out of the system, including conduction, convection, and radiation. Once the electro-thermal analysis is done, a thermal network model is derived based on reduced state-space approximations. The electrothermal flow is depicted in Figure 3 below.

The system co-design involved the concurrent physical and electrical design of each of the components (viz. die + package + pcb) while taking into account the impact of each on the system's key figure of merits performance. As stated in [10], sensing current by measuring voltage across a resistor is simple and elegant, but electrical and thermal issues arise that need to be addressed earlier in the design process. The system accuracy is impacted by many variables that lead to cumulative errors if not handled appropriately. On the silicon side, the input voltage offset, the offset voltage drift, common-mode rejection, the gain error, and input offset current of the amplifier, are among the key figure of merits (FOMs) that can impact accuracy [1]. Figure 2 shows the operational amplifier measuring the differential voltage developed across the shunt resistor and sending the amplified signal to the single ended ADC. Sensitivity of the amplifier is very critical in the signal chain. Performance optimization is achieved by ensuring minimal, to none, parasitics excursions in the system (viz. package and PCB) to the input of the amplifier.

DC resistance, a key figure of merit for package and PCB performance, was performed using a 3D quasi-static parasitic solver as per the electrical conduction analysis flow. Figure 4.0 below shows the set-up for package resistance model extraction. Four terminals are defined in the model. P1 is the current input node. P4 is the current output node. P2 and P3 are the differential sense pins. 4-port DC resistance model is extracted and employed in the circuit analysis. DC current is injected from P1 then the sense voltage, V_sense is probed between P2 and P3 in the circuit simulation set-up to extract the DC resistance.

In addition to DC resistance extraction, current density analysis is employed to making sure optimal field potential are achieved at the Kelvin sense pads (see Figure 5 below).

Optimizing DC resistance, under high volume manufacturing (HVM) process variations, is critical to the system performance. To that end, multiple designs of experiments (DOE) cases were set-up built to assess the impact on DC resistance of the low-Ohmic shunt and lead frame designs. The key design parametric sweeping for the low-Ohmic shunt design include - the shunt width, shunt material type, shunt resistivity variation (upper and lower bound), sense pad pitch, among others (Table I). Shunt width varies from 1.3 to 1.445 mm. Sense pad pitch varies from 1.215 mm to 1.365 mm. The target simulated DC_R value is 2 mOhm by design.

Once DC resistance optimized, the next step in the flow (see Figure 3) involved the electrothermal Joule heating (heat conduction + CFD) coupled analysis was performed. Fig. 6.0 shows the ET co-simulation setup for the system. The package design is physically merged with the physical design of the PCB. Fifteen amp of current is injected on one end of the PCB and output on the other end. The current flows through the lead frame onto the shunt resistor and is exited on the other side of the lead frame. Appropriate ET boundary conditions were employed for the ET analysis.

The minimum and maximum temperature of key components of the system, such as the shunt resistor, package mold, and controller were monitored during the ET analysis. Package lead frame and PCB layout were further optimized, based on the ET co-simulation results, to improve thermal dissipation and to assess impact to controller's junction temperature under high volume manufacturing process variations (see Figure 7).

The coupled electrothermal methodology was verified with silicon measurements and good correlation was observed for both electrical and thermal solvers. Table II shows a summary of the correlation for both electrical and thermal. The sense resistance is measured at 1.998 mOhm, while simulation estimate was 2.098 mOhm. The minimum and maximum temperature correlates very well between the measurement and simulation.

The thermal measurements set-up is shown in Figure 8 (top picture). A DuraCam XT IR camera with high resolution was employed. For correlation activities, the package was assembled on a dedicated EVM and measurements carried out at 23degC ambient. The middle and bottom pictures show the measurement and simulation results respectively.

Using co-design methodology it was demonstrated that good correlation between measurement and simulation can be achieved. TI's current solution is integrating the low-Ohmic shunt in package which can achieve current sensing inaccuracy to less than 1%. The benefits of integrating the shunt resistor in the package include (a) avoiding using extremely complex, high accuracy controller, (b) allowing higher accuracy 1% max over temperature, (c) to reduce the form factor, and (d) to provide a complete, accurate, and yet cost-effective solution.

The authors would like to thank Alan Chadwick and the technicians of the Founders Labs for their great support in collecting the thermal plots and providing all the support with the measurements set-up.