Reliability of Fan-Out Wafer-Level Heterogeneous Integration Open Access

Reliability of an interconnect such as solder joint, RDL, etc. of a particular package in an electronic product is defined as the probability that the interconnect will perform its intended function for a specified period under a given operating condition without failure [1–4]. Numerically speaking, reliability is the percent of survivors; that is, R(x) = 1 – F(x), where R(x) is the reliability (survival) function and F(x) is the life distribution function of the interconnect population. Thus, the one and only way to determine the interconnect reliability is by reliability testing to determine the F(x).

The life distributions of fan-out packages with a single chip under thermal cycling and/or drop conditions have been given by [5–9]. In [5] STATSChipPac performed the thermal cycling test of their 10mm×10mm eWLB-PoP (embedded wafer level ball grid array – package-on-package) on a PCB and the Weibull life distribution is given. Their test condition is from −40°C to +125°C and 2 cycles per hour. Their results show that the first failure occurred after 1000 cycles and the characteristic life (63.2% failure) is 1500 cycles. They also performed drop test and the characteristic life is 320 drops.

In [6], STMicroelectronics and STATSChipPac performed the thermal cycling test and drop test of package sizes (3mm×3mm and 2.4mm×2.4mm) and the corresponding chip sizes (2mm×2mm and 1mm×1mm) on a PCB. Their results show that the smaller the package and die sizes the better the solder joint reliability.

In [7], NANIUM (now Amkor) performed the thermal cycling test and drop test of their package (9.25mm×8.8mm) with a die size = 5.6mm×5.3mm on a PCB. Their thermal cycling test condition is from −40°C to 125°C, 1 cycle per hour, and their results show that the characteristic life is 1283 cycles. Their drop test condition is 1500G/0.5ms and the results show that the characteristic life is 1,161 drops.

In [8], SPIL performed the drop test of their package (9mm×9mm) on a PCB. Their drop test condition is 1500G/ms and the results show that the characteristic life is 566 drops.

In [9], STMicroelectronics and STATSChipPac performed the thermal cycling test of a package (9mm×9mm) with a chip (6mm×6mm) on a PCB. Their test condition is from −40°C to +125°C and 2 cycles per hour. Their results show that the characteristic life is 2600 cycles.

The life distributions of fan-out packages with multiple chips and capacitors under thermal cycling and drop conditions do not exist in the literature and are experimentally investigated is this study. The package size is 10mm×10mm and is housing one larger chip of 5mm×5mm, three smaller chips of 3mm×3mm, and 4 capacitors (0402). Nonlinear 3D finite element modeling and analysis are also presented. The experimental results and simulation results are correlated.

Figure 1 shows the test chips under consideration. The layout and fabricated large test chip is shown in Figure 1(a). It can be seen that the large chip dimensions are 5mm×5mm×150μm and there are 160 pads with a pitch = 100μm (the inner rows). The layout and fabricated small test chip is shown in Figure 1(b). The dimensions of the small chip are 3mm×3mm×150μm. It can be seen that there are 80 pads and are on 100μm-pitch (inner rows).

Figure 2 schematically shows the test package under consideration. Its dimensions are: 10mm×10mm and it consists of one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 (0402) capacitors. The spacing (gap) between the large chip and the small chip is 100μm. These packages are to be made from a 300mm metal reconstituted wafer as shown in Figure 2(a). The pitch of the test package on the wafer is 10.2mm.

Figure 3 schematically shows the cross-sectional view of the test package. There are 2 RDLs and the thickness of the metal of RDL1 is 3μm and of RDL2 is 7.5μm. The line width and spacing of the metal of RDL1 are 10μm and those of RDL2 are 15μm, respectively. The dielectric layer thickness of DL1and DL2 is 5μm, and DL3 is 10μm. The via (VC1), through the first dielectric layer (DL1), connecting the Cu contact-pad of the test chip to the first RDL (RDL1) is 20–30μm in diameter. The pad-diameter on the metal of RDL1 is 55μm, which is connected to RDL2 through the via (V₁₂) with a diameter of 30–40μm. The pad-diameter on the metal of RDL2 is 65μm. Finally, 220μm solder-ball Cu pads are formed on the metal of RDL2. The passivation opening (DL3) is 180μm. The solder ball size and pitch are 200μm and 0.4mm.

Figure 4 shows schematically the conventional FOWLP with chip-first and die face-down assembly process [10]. Basically, works must be done on the device (test chip) wafer, left-hand side of Figure 4, and the temporary reconstituted wafer, Figures 4(a) – 4(f).

First, test for KGD (known good die) of the device wafer. Then dice the wafer into individual KGDs or chips.

Figures 4(a) through 4(f) show the conventional FOWLP with chip-first and die face-down process steps on the reconstituted wafer. First, pick and place the KGDs face-down on a temporary carrier with a double-sided thermal release tape. Then, the reconstituted carrier with the KGDs is molded with EMC by using the compression method before removing the carrier and the double-sided tape and turning the whole reconstituted carrier around. Next comes building the RDLs on the Al or Cu pads. Finally, solder balls are mounted and the whole molding is diced into individual packages.

In the present study, we will not use the conventional method such as Figures 4(d)–4(f) to build the RDLs. Instead, we will use the new process shown in Figure 5.

In the conventional FOWLP, after debonding the carrier and peeling off the tape, Figure 4(d), the total thickness of the reconstituted wafer is usually ≥ 450μm. It is followed by building the RDLs and mounting the solder balls, Figure 4(e). However, in this study, in order to save the expensive EMC materials and have a very low profile package, the total thickness of our reconstituted wafer without the carrier is only 300μm, which is too fragile to fabricate the RDLs and mount the solder balls.

One of the solutions is to attach the thin reconstituted wafer on another temporary glass wafer with a coated LTHC (light-to-heat-conversion) layer as shown in Figure 5(a) and then remove the metal carrier and peel off the tape, Figure 5(b). It is followed by making the RDLs as shown in Figure 5(c) with the method shown below.

Figure 6 shows the key process steps in making the RDLs. First, spin coat a photosensitive polyimide (PI) on the reconstituted wafer. Then apply a stepper (every 4 test packages as a unit) and use photolithography techniques to align, expose, and develop the vias of the PI. Finally, cure the PI at 200°C for one hour. This will form a 4 to 5-μm-thick PI layer. (PI development.) It is followed by Sputtering Ti and Cu by physical vapor deposition (175 to 200°C) over the entire wafer. Apply a photoresist and a stepper and then use photolithography techniques to open the redistribution-traces locations. Then electroplate Cu by electrochemical deposition (room temperature) on Ti/Cu in photoresist openings. Strip off the photoresist and etch off the Ti/Cu. (RDL1 is obtained.) Repeat the above steps to obtain RDL2.

There are two different stencils for the solder ball mounting, one is for stencil printing the flux and the other is for stencil mounting the solder balls. The solder (Sn3wt%Ag0.5wt%Cu) balls (200μm-diameter) used are from Indium and are on 0.4mm-pitch. The peak temperature for solder reflow is 245°C.

The de-bonding of the glass carrier as shown in Figure 5(d) is by scanning a laser (355nm DPSS Nd: YAG UV laser source is used) from the glass carrier side. The laser spot-size is 240μm, the scanning speed is 500mm/s and the scanning pitch is 100μm. When the LTHC layer “sees” the laser light, it converts into powders and the glass carrier is easily removed. It is followed by chemical cleaning. The reconstituted wafer is diced into individual packages as shown in the x-ray image in Figure 7, where also shows the metal of RDL1 and RDL2 of the package.

The PCB and stencil design will be briefly mentioned. The stencil solder paste printing, pick and place, and solder reflow will also be presented. The x-ray images and the cross section images of the PCB assembly are provided.

The PCB for the fan-out package is made of FR-4 and is shown in Figure 8. It can be seen that there are 4 package sites on the board. The dimensions of the PCB are 103mm×52mm×0.65mm and there are 6 layers. There are 405pads (with a pitch = 0.4mm) for each package. The pad with a diameter = 0.2mm is non-solder mask defined and its surface finish is OSP (organic solderability preservative). The solder mask opening diameter is 0.28mm.

The stencil is made of stainless steel with a grain size of 2μm (which will benefit for the solder paste transfer) and is 0.08mm-thick. The opening is fabricated by laser and electrical/chemical polishing. The opening is increased from a 0.2286-mm-diameter circle to a 0.2413-mm² square (a paste volume increased by 41.8%). The solder paste printing is by the DEK Horizon 9.

The pick and place is by the SiPlace ×4s. The 10 temperature zones BYU Pyram nitrogen 150N is used for the reflow. The temperature profile is shown in Figure 9. It can be seen that the maximum temperature is 245°C and the time above 217°C is 85 seconds.

Fifteen boards (each with 4 packages) are used for the temperature cycling tests. The sample size is 60 packages. Thermal cycling is performed in a Votsch 7027-15 environmental chamber. This unit is capable of achieving chamber temperature as high as 190°C and as low as −70°C. Heating and cooling are achieved by forced convection, and the maximum ramp rate is 15°C per minute. All of the boards are placed vertically in the chamber as shown Figure 10. The temperature input to the chamber (measured in the air of the chamber) is shown in Figure 10. It can be seen that the temperature cycling is from room temperature to 85°C and stay there for 15 minutes, then ramp down to −40°C and stay there for 15 minutes, then ramp up to 85°C and stay there for 15 minutes, and so for. The ramp up and ramp down times are 15 minutes each. The acquisition system is an Agilent 30970A data logger.

The thermal cycling test results of the FOWLP solder joint (without underfill) reliability are shown in Figure 11. The thermal cycling test stops at 1,300 cycles. It can be seen that the characteristic life (63.2% failed) of the Weibull plot is 1,070 cycles which is more than adequate for the expecting life (usually is less than 3 years) of mobile products such as the smartphones and tablets. The failure location and mode are shown in Figures 12 and 13. It can be seen that the solder joint cracks near the interface between the bulk solder and the package contact pad and it occurs under the chips' corners near the package corners – the longest DNP (distance to neutral point) [11].

The test setup is according to JEDEC Standard JESD22-B111 as shown in Figure 14. After more than 20 tries, the right height of the drop table is obtained which yields the specified G levels and pulse duration (1500Gs, 0.5 millisecond half-sine pulse) as shown in Figure 15.

There are 24 samples with underfill. The material properties of the underfill are: the filler content = 25%, the maximum filler size = 5μm, the average filler size = 1–2μm, the curing time and curing temperature = 8 minutes @ 135°C or 5 minutes @ 150°C. The Young's modulus, Poisson's ratio, and CTE are respectively, 4–5GPa, 0.35, and 50–52×10⁻⁶/°C. The drop condition is 1,000 drops. After more than three weeks of drop tests, all these 24 samples passed 1000 drops. Thus, the fabricated package samples in this study are considered reliable under drop condition.

From a scientific point of view, unfortunately the test stops after 1000 drops, thus there is not any failure data to determine a life distribution and consequently the characteristic life, etc. On the other hand, due to resource availability, we cannot let the drop tests going for longer.

The PCB assembly of the fan-out SiP shown in Figures 7 and 9 is modeled as a 3D strip that captures the construction along a diagonal path from the assembly (Figure 16). Due to the symmetry about the vertical midplane of a full strip, the model is actually a half-strip with the appropriate in-place restraints placed on one symmetry plane. Coupled in-plane translations are applied to the other symmetry plane to produce a state of generalized plane strain. Using exclusively hexahedral solid elements, the model can capture the precise shape of the packages' solder joint and potential DNP effects while retaining significant computational efficiency over full octant models.

Despite the overall economy of elements in the strip model, selective mesh refinement is used to concentrate highly refined elements in the solder joints where failure is anticipated. In the present PCB assembly, failure would be predicted in the solder joints with the greatest DNP (the package corner) and near the chip corners as shown in Figure 16. Thus, highly refined meshes are applied to these solder joints. The other solder joints are coarsely meshed. The ABAQUS 6.12 (C3D8R) is used for the model.

The material properties of the PCB assembly shown in Figures 7 and 9 are shown in Table I. All the material properties are assumed to be constant except for those of solder. The Sn3wt%Ag0.5wt%Cu is assumed to follow the generalized Garofalo creep equation [4]:

where ɛ is the strain, σ is the stress in Pa, and T is the temperature in Kevin. The CTE and Young's modulus of the solder are respectively, 21.3+0.017T and 49-0.07T, and T is the temperature in Celsius.

The temperature profile shown in Figure 10 is to be imposed on the PCB assembly. Five temperature cycles are executed.

Figure 17 shows the shear stress and creep shear strain hysteresis loops at the solder joint under the 3×3 chip corner. It can be seen that after three cycles, the creep responses converged (become stabilized). Similar results are observed at the solder joint of the 5×5 chip corner. The largest Mises stress and accumulated creep strain occur at the solder joint under the 3mm×3mm chip corner as shown in Figures 18 and 19. The location is at the interface between the bottom of the package and the bulk solder. Thus, any failure should occur at this location. This correlates very well with the thermal cycling test failure location and mode as shown in Figure 12. The second largest Mises stress and accumulated creep strain occur at the solder joint under the 5mm×5mm chip corner as shown in Figure 18 and 19. Again, this correlates very well with the thermal cycling test failure location and mode as shown in Figure 13. The maximum Mises stress (7.415×10⁷ Pa, Figure 18) occurs at −40°C during the thermal cycling condition shown in Figure 10. The maximum deformed shape (4.83×10⁻³ mm) of the strip model at −40°C is shown in Figure 20.

The accumulated creep strain vs. time is shown in Figure 21. It can be seen that the creep strain per cycle is equal to 0.018, which is too small to create solder joint reliability problem, especially for mobile products such as smartphones, which life is less than three years.

The finite element model for drop test with underfill is shown in Figure 22. It can be seen that, for simplicity, there is only one package at the center of the PCB and the package is subjected to the acceleration shown in Figure 15.

During impact, the most likely failure location is the RDLs near the package corners and the most likely failure mode Is the broken Cu wire in the RDLs. Thus, finer meshes are applied to the Cu wire of RDLs near the package corner as shown in Figure 23.

The material properties for drop analysis are shown in Table II. Since the focus of this analysis is not on the solder joint thus all the materials are assumed to be constant. The ABAQUS explicit solver is applied for the simulation. Thus, the damping effect is included through the bulk viscosity method in ABAQUS explicit solver. The damping coefficients b₁ and b₂ applied in the analysis are assumed to be respectively, 0.02 and 0.

The applied acceleration is shown in Figure 15 and Figure 24. The time step for the calculation is 1×10⁻⁸ second. The time-histories of strain in the x-direction (ɛ₁₁) and y-direction (ɛ₂₂) and the maximum principal strain acting at the RDL of the package corner near the 5mm×5mm chip are shown in Figure 25. Basically, the ɛ₁₁ and the principal strain are the same, i.e., the strain is dominated in the x-direction. The maximum deflection (2.783mm) of the PCB assembly occurs at the 0.0022 second (Figure 25) and is shown in Figure 26. The maximum principal strain = 0.0023 is also occurred at that time. The deflection and strains are decreasing with time due to the damping of the structure as shown in Figure 25.

The maximum Mises stress occurs (Figure 27) at the same location (i.e., at the Cu wiring of RDL near the package corner of the 5mm×5mm chip) as the maximum principal strain as shown in Figure 25 and is equals to 3.546×10⁸ Pa. Thus, any failure should occur at this location.

Some important results and recommendations are summarized as follows.

• ➢ Thermal-cycling and shock reliability performances of chip-first and die face-down fan-out heterogeneous integration of one large (5mm×5mm) chip, three small (3mm×3mm) chips, and four (0402) capacitors embedded in an EMC package (10mm×10mm) with tow RDLs have been experimentally determined.

• ➢ The characteristic life of the solder joints without underfill under thermal cycling test has been estimated to be 1,070 cycles. This is more than adequate for most mobile products such as smartphones and tablets, whose life is usually less than three years.

• ➢ The failure locations of the solder joints have been found to be at: (a) the solder joint near the package corner and under the 3mm×3mm chip corner along the diagonal direction of the large and small chips, and (b) the solder joint near the package corner and under the 5mm×5mm chip corner.

• ➢ The failure mode of the solder joints without underfill has been found to be cracking between the Cu-pad of the package and the bulk solder of the solder joint.

• ➢ Creep of solder joints under thermal cycling condition has been determined by non-linear and time dependent 3D finite element simulation. Five temperature cycles have been executed and the hysteresis loops have been shown that the creep behavior has been stabilized after the third temperature cycle. The maximum creep strain and Mises stress have been found to be occurred near the interface between the bulk solder and the Cu-pad under the chip corners near the package corners and along the diagonal of the large and small chips. These failure locations and mode correlated very well with the experimental results (failure locations and mode.)

• ➢ As expected, the DNP concept works for thermal cycling. The most outer two diagonal solder joints from all 4 package corners have been removed from the present study. It would be even better if the solder joint under the larger chip corner and the solder joint under the small chip corner (along the diagonal direction of the large and small chips) are removed.

• ➢ PCB assembly of the heterogeneous integration package with underfill has been through the drop test with an acceleration spectrum intensity = 1500G/ms (1500Gs, 0.5 millisecond half-sine pulse). All 24 samples passed 1000 drops. Thus, the fabricated RDLs of the package are reliable for mobile application.

• ➢ Shock of the heterogeneous integration package RDLs under the given drop condition has been determined by time-history analysis. It has been found that due to the structural damping, the dynamic responses are decreasing with time. The maximum stress (3.546×10⁸ Pa) and strain (0.0023) occurred at 0.0022 seconds after the impact. The location of the maximum stress and strain has been found to be at the Cu conductor wiring of RDL2 near the package corner and the 5mm×5mm chip corner.

• ➢ Unfortunately, the characteristic life of the RDLs cannot be estimated from the drop test, which stopped right after 1,000 drops of each sample, without failure.

The authors would like to thank their managements from ASM, DOW, Huawei, Indium, JCAP, and Unimicron for their strong support of this consortium project.