Enabling High-Performance Heterogeneous Integration via Interface Standards, IP Reuse, and Modular Design Open Access

The DARPA Microsystems Technology Office (MTO) has driven the development of revolutionary materials, devices, and integration techniques to meet the performance requirements for the most advanced electronic systems [1,2]. In particular, the Compound Semiconductor Materials on Silicon (COSMOS) program focused on the development of new methods to tightly integrate compound semiconductor (CS) technologies within state-of-the-art silicon CMOS circuits in order to achieve unprecedented circuit performance levels [3–8]. More recently, the Diverse Accessible Heterogeneous Integration (DAHI) program continued that work by developing heterogeneous integration processes to combine advanced CS devices and other devices with high-density silicon CMOS in a foundry setting [9–13]. These programs demonstrated the benefits of heterogeneous integration in defense applications while solving fundamental technical issues to set the stage for further progress.

Now, DARPA is working to extend mainstream semiconductor design infrastructure for rapid and cost-effective integration of heterogeneous device technologies. This represents a significant step past the monolithic silicon approach that has stalled in the face of prohibitive cost and design issues at leading-edge nodes. The path to higher performance requires a broader set of feasible device technology options. DARPA's Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program will address these challenges by developing interface standards, IP reuse methodologies, and modular design approaches with the goal of making heterogeneous integration as straightforward as printed circuit board design and assembly, without compromising device performance [14,15].

To enable the vision of seamless integration of diverse device technologies, interface standards are needed to foster a CHIPS eco-system. The CHIPS methodology will be adopted only if designers throughout the industry can design chiplets to a known interface standard. (Additionally, the existence of a CHIPS standard will be a self-reinforcing scenario – the use of the standard by chip designers will broaden its utility, thus encouraging more designers to make use of it.) While there are numerous parallel and serial interface standards in the industry, they are typically for specific functions, such as the High Bandwidth Memory (HBM) DRAM standard codified in JEDEC's JESD235A standard. The CHIPS program is driving convergence on an interface standard that will likely leverage existing standards but is also tailored for the specific technical requirements of connecting chiplets in applications that can benefit the most from modularization.

The second pillar of the CHIPS approach is IP reuse. To save time and money – measured in years and millions of dollars – it is typical in monolithic chip design to reuse verified IP blocks for common functions. For heterogeneous systems, though, this IP infrastructure is lacking because of the increasingly complex challenges when multiple technologies are integrated. With a standard CHIPS interface for heterogeneous integration, IP reuse is enabled at the chiplet level. Heterogeneous design will become essentially the same as monolithic design, with the knowledge that IP blocks can be integrated successfully.

Finally, a modular design paradigm is needed to enable designers to take full advantage of interface standards and heterogeneous IP reuse. Design tools and process design kits (PDKs) will account for different device technologies and their integration, with the appropriate design, simulation, and analysis capabilities in place.

The CHIPS program metrics are summarized in Table I.

The CHIPS program is structured in two Technical Areas (TAs) – Modular Digital Systems (TA1) and Supporting Technologies (TA3). System performers are Boeing, Intel, Lockheed Martin, Northrop Grumman, and the University of Michigan. Each of the System performers is designing a system using the CHIPS approach, and the teams are also collaborating to specify and implement an interface standard. Since convergence on the interface standard is required before designs can be finalized, this is the first major milestone in the CHIPS program. The definition of the CHIPS interface standard is being rolled out to the industry in 2018.

The Supporting Technologies performers will provide IP blocks and design tools that will be used by System designers, although the IP blocks and design tools will be developed with broader usage in mind. Performers developing design tools are Georgia Tech and Cadence, while IP blocks are being developed by Intrinsix, Jariet Technologies, Micron Technology, North Carolina State University, and Synopsys. The System designers will also be providing IP blocks.

To ensure successful integration, the CHIPS program is also pursuing multiple integration strategies. The first will be a leading edge but broadly available industry standard interconnect on a silicon interposer, while at least one other approach with much finer pitch will be developed in parallel for Phase 2 of the four-year program. Early results on new integration technology are expected in 2018.

The performers in the CHIPS program have agreed to base the CHIPS interface standard on Intel's Advanced Interface Bus (AIB) standard. This was enabled by Intel offering a paid-up, royalty-free license for the relevant IP and documentation. After extensive discussion and debate among the CHIPS performers, AIB was chosen as the basis for the CHIPS interface. The key factors in that decision were: 1) performance metrics (Table II) that meet the CHIPS requirements, 2) the flexibility to meet a range of applications, with CHIPS-specific “lite” and “turbo” options, for example, and 3) silicon-proven maturity based on Intel's use of AIB. The I/O cell and details of the clock forwarding architecture are shown in Figure 1.

The success of the CHIPS program depends on creating a set of IP blocks with numerous applications, since a key part of the CHIPS premise is reuse of common IP blocks. The CHIPS program has selected several performers to provide IP blocks for the program, whether for their own system demonstrations or for use by others in the program. Chiplets currently being designed and manufactured in Phase 1 and those under consideration for Phase 2 are summarized in Table III.

The chiplet sizes range from approximately 0.5mm² to 15mm², with most being 1–4mm². Plans for chiplet fabrication include leveraging multi-project wafer (MPW) runs at GlobalFoundries (14nm, 32nm, and 65nm) and TSMC (16nm node via DARPA's CRAFT program).

Design tools for a vertically-integrated design flow for IP reuse and heterogeneous integration are under development by Georgia Tech. That team's tasks include protocol implementation, analysis of chiplet options, interposer routing analysis, and power delivery network analysis. A sample analysis indicates a 33% reduction in power with an integrated voltage regulator chiplet, and the voltage response in that scenario is shown in Figure 2.

Cadence Design Systems is contributing to the CHIPS design environment by creating models of different interconnect schemes and verifying them with measurements performed by NIST. Their studies are covering organic and silicon interposer options, and initial models of noise margin and jitter margin show the impact of cross-talk (Figure 3), which is a useful tool for designers.

The pieces of the CHIPS program are being brought together in a phased sequence of demonstrations: Phase 1 interface functionality, Phase 2 modular systems, and Phase 3 rapid modular system upgrade. A number of teams are developing systems with the CHIPS approach.

Intel is developing a platform based on its Stratix-10 FPGA, which enables a wide range of applications, including those that leverage machine learning. The CHIPS interface based on Intel's AIB is used to connect the FPGA to various chiplets (e.g., data converters, ASICs, processors, and analog functions), and memory can be integrated with other standard interfaces. The concept is shown in Figure 4.

The CHIPS team at the University of Michigan has made rapid progress with its first set of chiplets being taped-out in April 2018 for a 16nm MPW run at TSMC via DARPA's CRAFT (Circuit Realization at Faster Timescales) program. This includes a deep neural network (DNN) accelerator and neuro-coding chiplets for visual processing applications, as well as the first CHIPS instantiation of the AIB-based interface (Figure 5).

Lockheed Martin Advanced Technology Laboratories has proposed an application that addresses a spectrum of common DoD challenges [16]. Along with the inherent cost reduction of decreasing the total design and manufacturing effort required for system upgrades, the CHIPS approach improves reliability, qualification cost and time, and diminishing manufacturing source (DMS) challenges. With a modular electronics sub-system based on IP reuse and standard interfaces, it is possible to swap in just the components that need an upgrade, thus preventing a total overhaul of the system to retain leading-edge performance. This is particularly critical for applications with life cycles measured in decades, such as aircraft. Lockheed is pursuing this approach in a network interface unit in a major avionics platform.

Northrop Grumman Mission Systems (NGMS) is also pursuing CHIPS-based systems for defense applications and has identified digital transceivers as an application that could benefit from a chiplet-based approach. By separating the SoC into separate functions, it is possible to optimize the device node and even the foundry source. Their analysis shows a 74% reduction in NRE and 70% reduction in development time by buying and assembling chiplets rather than buying, integrating, and manufacturing the required IP [17]. For this application, a key enabling technology for SoC disaggregation is sub-10μm interconnect pitch, and NGMS is working with Micross to develop this, as described in Section VII.

Early in the CHIPS program, the performers settled on 55μm Cu pillar interconnect as the primary path, since this represents the finest pitch interconnect that has an established supply chain and user base. As the first step in the CHIPS program, it is a convenient compromise using leading-edge but broadly available technology.

In parallel, two CHIPS teams are developing alternative interconnect approaches with much finer pitch interconnect to extend the CHIPS roadmap well into the future. Micross and NGMS are collaborating on ultra-fine-pitch interconnect, which NGMS has shown to be a critical enabler for their target applications. Micross has demonstrated both Cu and Au metallurgies for 10μm and below pitch (Figure 6) with non-collapsible bumps [18]. This work will continue in CHIPS to demonstrate finer pitch interconnect, compatibility with advances nodes, and reliability.

A team at the Center for Heterogeneous Integration and Performance Scaling at UCLA is also developing sub-10μm interconnect for CHIPS. They have demonstrated Au-capped Cu pillar interconnect at 10μm pitch (Figure 7) and have roadmap options to eliminate the Au cap and decrease the pitch further. A novel part of UCLA's approach is the use of a silicon wafer as the substrate. This Silicon Interconnect Fabric (Si-IF) provides performance and mechanical advantages, and UCLA is developing system-level approaches for integrating the Si-IF.

The interconnect strategy is a critical part of the CHIPS eco-system. Along with the technical capabilities for fine-pitch interconnect, there also needs to be access to foundries, MPW runs, volume assembly, PDKs, and other critical supply chain capabilities. DARPA is paving the way for some of this, but the eco-system also needs industry support that arises from the market potential of the CHIPS approach. In parallel, business models that fill new needs in the CHIPS eco-system are being explored. For example, silicon IP companies are pursuing the option of becoming chiplet suppliers. Instead of just providing soft or even hard IP, they will sell verified chiplets ready for assembly. This is a perfect illustration of the innovation brought by the CHIPS approach to the semiconductor marketplace.

DARPA's CHIPS program aims to serve as the necessary piece of the puzzle that lets heterogeneous integration gain momentum in the marketplace by leveraging proven approaches of the semiconductor industry. With advantages for both defense and commercial applications, a critical mass of CHIPS adopters is expected.

The industry has recognized the great challenges before us in IEEE's newly revamped International Roadmap for Devices and Systems [19], and an important step was made when the IEEE, SEMI, and ASME jointly established the Heterogeneous Integration Roadmap [20] in recognition of the importance of heterogeneous integration to the solution set for these upcoming challenges. In this spirit, DARPA has been at the forefront of heterogeneous integration for many years and is now focused on enabling the traction needed to drive broad adoption via the CHIPS program. The progress and interest level shown so far by defense and commercial players suggest that this is a valuable approach.

The authors thank the DARPA program managers and staff who have contributed to the formulation and progress of the CHIPS program, particularly Kang Lee for compiling and tracking metrics and IP data. Acknowledgment is also due to the performers who are executing the CHIPS vision for DARPA.