Bumping Process Impact on the Chip Package Interaction (CPI) Reliability Open Access

As the technology advances, the interconnect structure continues to evolve with decreasing dimensions and increasing number of layers and complexity. The reduction in feature size, however, degrades the interconnect RC delay, which tends to curtail the benefits of interconnect scaling. The semiconductor industry is now focusing its efforts on implementing ultra low K (ULK) or extreme low K (ELK) porous dielectric materials (k < 2.5) into Cu interconnects to reduce the interconnect capacitance and cross-talk noise and enhance circuit performance [1, 2]. However, the introduction of these fragile ULK/ELK materials coupled with the legal requirement to remove lead containing materials from the chip and package presents significant challenges to product reliability due to the weak mechanical properties of ULK/ELK materials interacting with rigid lead-free bumps. With huge effort spent by the foundries, the mechanical properties have been improved significantly with optimized ULK/ELK process.

Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Many works have been done from ULK/ELK process, BEOL stacks, FBEOL optimization, assembly reflow profile, underfill selection to improve CPI reliability [2–6].

Controlled collapse chip connection (C4) bump technology has been widely used in flip chip package technology and provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is also very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability.

In this paper, we focused on SnAg bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

Figure 1 showed the normal C4 bumping process flow. It starts with PI process including PI coating, develop and cure, followed by sputtering UBM seed layers like Ti and Cu, then photo resist coating, bake and patterning, Ni/solder plating, photo resist striping, then UBM etching to remove UBM seed layer beyond bump region, the last step is reflow to form the spherical shape of the bump. Final inspection and measurement will be done before shipping to assembly.

We will follow the process flow to discuss the bumping process impact on the CPI reliability.

During the bumping process, Particles are one of the killer to cause CPI reliability failure. One short failure encountered during reliability test during our CPI qualification. Failure analysis (Figure 2) showed the solder diffused into the Cu pad and form Cu IMC with volume expansion which broke the passivation and ILD. The solder continues diffusion to the other line or layer and induces short. EDX mapping analysis showed that no UBM (Ti) found in the diffusion location of the bump.

The suspected root cause is that foreign particles dropped on Cu pad surface after PI develop and before UBM sputtering, Ti/Cu deposits on the particles. Particles were flushed away by removal of PR process and cleaning, and leave a hole on the Cu pad, after solder plating, and reflow, solder direct exposed to the Cu pad to form IMC (Cu3Sn/Cu6Sn5) and Sn continue diffuse into the Cu rapidly during reliability test. Figure 3 showed the schematic of the root cause of missing Ti/Cu UBM seed layer on the Cu pad. Cu IMC volume expands inducing higher local stress to break passivation and ILD. SnCu IMC sneaks into the crack to reach other contact and cause short failure. The regular inspection tool resolution was set to 10um for the particles, so the particles size smaller than 10um can't be captured during the inspection. In order to catch smaller particles, 4um inspection resolution setting has been applied during the inspection. Inspection results proved that the smaller particles escaped by 10um resolution setting and captured by 4um resolution setting. Table 1 listed the inspection summary. Solving the particles issue, high resolution inspection tool has been selected to detect smaller size of particles, and HEPA installed to prevent particle during the bumping process.

Ti UBM seed layer also acts as the barrier layer to prevent solder diffusion into the terminal pad. The thickness of Ti deposition and the shape of the passivation opening will impact the CPI reliability. In general, UBM thickness on the sidewall of passivation opening is thinner than UBM thickness on bottom of the pad. If Ti layer is too thin, it will break because of the high local stress induced during the stress test. Solder will diffuse into the Cu pad through the cracked Ti seed layer, and form Cu IMC. IMC will expand the volume to crack ILD layer and diffuse further to the neighbors causing short failure. Figure 4 is the FIB X-section of the failure bump after the stress test. It showed the non-continuous or broken UBM (Ti) at the sidewall of the passivation, and Sn diffused into the Cu pad and form Cu_xSn_y IMC on the terminal metal pad causing the volume expansion. It is very critical to control Ti thickness during Ti deposition. The profile of the passivation side wall is also important and should be well controlled to prevent such fails.

UBM undercut is almost inevitable during the bumping process. UBM undercut must be tightly controlled to avoid any CPI failures. In our early CPI development work, white bumps were observed after assembly. Figure 5 is the CSAM image of the failures which showed white bumps at the die corner area. FIB x-section has been done to find the failure signature. It found that the Polyimide crack start at the end of UBM undercut, propagated into the passivation to crack the passivation, and further through ILD and causing ILD crack (Figure 6). The UBM undercut of the failed bump is about 9.2um. FEA modeling also run to evaluate the risk with different size of UBM undercut. In the simulation, no UBM undercut, 2um, 5um and 10um undercut have been assessed on ULK/ELKstress. The results showed that the normalized ULK/ELK stress has been increased 6%, 8% and 11% with the UBM undercut of 2um, 5um and 10um respectively (Figure 7). UBM undercut control therefore becomes very critical in improving CPI reliability. We worked with bumping suppliers to develop new UBM etch process which reduces the UBM undercut significantly to ensure better CPI reliability performance.

One electrical short failure was found by package O/S test during CPI technology qualification. The failure was verified by curve trace. CSAM was used to identify the failure location as shown in Figure 8. P-lapping was done to bump UBM level and FIB x-section did not find any particles near the failed bump (Figure 9). FIB cross-section and EDX shows that UBM was almost absent in this region and Sn diffused into the top metal layer (Figure 10). Based on the FIB results, it can be confirmed that failure was not related to particles on the UBM. According to Unit ID (x–y coordinates), inspection report before plating has been reviewed. Bump defect map showed the dark color on the same bump location indicating the possible UBM seed layer oxidation (Figure 11). It was suspected that UBM seed layer oxidation was caused by dropping of photoresist developing chemical which resulted in poor Ni plating to form thin/incomplete Ni layer before solder plating. As such, the thin or missing Ni barrier layer cannot prevent Sn diffusion into top metal during reliability test. This failure can't be detected before reliability test and only captured by the electrical test during or after reliability test.

Verification experiments were conducted to validate the root cause of the failure. The process flow of DOE was shown in Figure 12. Ti/Cu UBM layer was sputtered on the wafer, then photo-resist (PR) applied and developed. A drop of PR developing chemical was dropped on the UBM opening, and kept for 30min, then inspected and sent to plated with Ni. Inspection was done again after Ni plating. The experiment inspection results of post PR development and post plating are shown in Table 2. The bump with PR developing chemical dropped on was discolored comparing to the other bumps without PR developing chemical on. This discolor of the bump matched the one of the defect map on the failing unit and meant the defect can be duplicated. The color is lighter of the PR chemical dropped bump than the other normal bumps after Ni plating. EDX analysis of normal UBM seed layer and discolored UBM seed layer disclosed higher atomic% of element O on discolored UBM seed layer indicating UBM seed layer oxidation by PR developing chemical (Table 3). Solder plating continued with the experiment wafer and whole bumping process completed. The die of experiment was mechanical X-sectioned. The result confirmed thinner or missing Ni on the brighter color pad, and normal Ni thickness on the dark pad. (Figure 15). The bump shape of brighter UBM is smaller than the normal one. The experimental results proved that oxidized seed layer by PR developing chemical was the root cause. The corrective action was taken to prevent PR developing chemical drop on the wafer after PR develop process. In-line monitoring inspection data showed seed layer oxidation defect rate reduced 6 times after corrective action in place. Furthermore, any UBM discoloration inspected during the bumping process will be inked out at final wafer map to eliminate the reliability risk.

One electrical short failure encountered during extended HTS reliability test. Non-destructive FA identified the failure location and P-lapping showed partial Ni at the failure bump location (Figure 14). FIB cross-section showed Ni was only partially plated (Figure 15). Further bump in-line defect correlation study indicated that incomplete Ni was related to partial PR opening (Fig. 16).

The root cause is that the photoresist opening damage resulted in partial Ni layer. The photoresist opening damage was suspected to be caused by particles. During PR exposure (PR EXP), particles on the PR surface blocked the PR exposure and PR remained in UBM opening area after PR develop. There is no Ni plated on the covered area, this bump also became abnormal after solder plating and reflow. The PR will be stripped away after PR removal, leaving Ti/Cu seed layer exposed. Cu and Ti seed layer will also be removed during UBM etch process to leave a hole on the Cu pad. After bump reflow, Solder bump directly flow on the Cu terminal pad. Figure 17 shows the schematic of how this defect formed during process. Without Ni and UBM layer protection, Sn diffused into Cu to form Cu_xSn_y IMC causing volume expansion which induced the high local stress to crack the ILD. Solder continue to diffuse through the ILD crack to neighbor trace and cause short failure during reliability test. The corrective action of particles prevention and detection has been implemented to reduce such failure.

As connection between Si and package, C4 bump and C4 bumping process played very important role on CPI reliability. SnAg bumping process effect on the CPI reliability has been focused in this paper. CPI reliability issues induced by the bumping process like particles on Cu pad, Ti seed layer deposition, UBM undercut, Cu pad oxidation, and photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability. The failures of high volume production reduced significantly after the implementation of corrective action.