Fine line panel level fan out changes the SiP landscape

Semiconductor scaling has been continued for the past few decades. Industries are working to put more functionalities into less footprint chips, while making it run faster, consume less power, and keep reducing cost. However the trend has faced challenges in recent years. The node evolution has extended from 18 months to 30 months or longer. The physical limitations and the vanished economical benefits after 28nm have constrained the advance of Moore's law. Leading foundries are still dedicated to “more Moore” solution, while the packaging companies are focusing on “more than Moore” solutions to extend the Moore's Law.

The SoC concept worked well for applications that required top-notch performance such as CPU and GPU. The drawback of SoC design is the long development time, high cost, and huge engineering resources. The situation is getting direr for any wafer node that is more advanced than 28 nm. This is somehow less of an issue for System in Package (SiP), where devices that required state-of-the-art wafer node can keep progressing with the Moore's Law, while the rest of the devices can stay with its most matured wafer node. The SiP solution can achieve better cost and time to market without significantly sacrificing the performance as compared to a SoC.

Fig. 1 shows the aforementioned concept of a SoC and a SiP, which can be seen as a virtual SoC. The CPU and GPU will keep up with the most advanced node to address the request of high performance, where matured wafer nodes are more than adequate for many fixed frequency devices like audio/video/image signal processor, WiFi, and others. However, advanced packaging technology is needed to interconnect these now individually fabricated chips to achieve SoC-like performance. There are several available technologies suitable to implement the SiP design, such as BGA SiP, 3D/2.5DIC, fan out on wafer level, and fan out on panel level.

Being one of the most well established technologies, BGA SiP is readily visible on the devices that consumers used on a daily basis. In a BGA SiP multiple chips are either wire-bonded or flip-chip bonded to the substrate with lots of passives. However, it has the limitation in line/space of the interconnection traces. This limits the package dimension shrinks and leads to increased power consumption and higher signal/power loss, especially if the device operates of a high frequency.

Unlike BGA SiP that uses a side-by-side configuration, 3DIC stacks chips vertically and electrically connects the chips with TSVs. TSV interconnection offers excellent electrical performance. However, there are restrictions with this design, such as increased complexity in chip design, thermal management, and process difficulty.

The 2.5DIC packaging also uses TSVs to connect chips, but the interconnection is realized horizontally. A silicon interposer is used as a substrate for the chips, and it is possible to achieve sub-micron traces on silicon, therefore providing very good electrical performance.

3DIC/2.5DIC is known for their excellent performances but the prices are also very steep, therefore mostly reserved for high end applications such as high speed computing.

The fan out package builds the fine L/S interconnections with the RDL technology. It eliminates the laminate substrate and can achieve finer L/S than the laminate substrate based process. It has benefits of better electrical performance, smaller form factor, higher I/O density, and lower power consumption than the conventional laminate substrate. Besides, everything is done on the wafer level; the chips were picked and placed on another wafer, also known as re-constitution wafer, where the rest of the packaging processes were performed.

Fan out on panel level is performed on the panel level. The geometry of the panel naturally allows more chips to be processed at a time, therefore the benefits of greater production efficiency and cost reduction. Normally the larger the package size the better the utilization rate for panel, since the panel is rectangular in geometry, nearly all the spaces on the panel can be utilized. In table I the package quantity ratio of panel over wafer is compared, one can easily see that the larger the package size, the better the ratio. Heterogeneous integration typically requires larger package size to accommodate multiple chips, thus this is a strong incentive for the industry to adopt the panel level fan out.

Wafer based semiconductor industry have universal standards made by SEMI for the supply chain to follow. On the other hand, no standards exist for the panel level fan out technology. This could bring challenges in deciding the necessary equipment and material specifications, both of which are required to co-develop with the vendors.

It is not easy to formulate a universal standard for panel level packaging because it is an emerging field of the semiconductor industry. A comparison of different industry's tools needs to be done before deciding the tools for panel level fan out. For example, the wafer foundry may have a unique edge on lithography and any wafer form processing, but their panel processing and warpage control capability were rather limited. The lithography process of the LCD industry, from coating to development, can be considered for adoption since they have existing experience with large sized panel and fine line capability. However, they have little experience with warpage control and packaging experience is non-existent. The deposition process could utilize both LCD's PVD tool or the expanded version of ECD from wafer level packaging and bumping tool.

In summary, many tools can be leveraged from existing technologies to constitute a complete panel assembly line, but some tools needed to be tailored and co-developed with equipment vendors.

Warpage is a physical phenomenon that occurs when thermal expansion coefficient mismatch exists between materials. The warpage is an undesirable side effect during processing and would only get worse with the increasing working size of the panel. The optimization of package structure, process parameters, and material property were needed to mitigate the negative impact of warpage. The optimization can be aided with computer simulation.

There are also other ways to make the warpage less of a problem during processes. For example, the warpage can be mechanically suppressed by using guide rollers on conveyor to ensure a smooth transportation of panels. And the clamps and vacuum chuck serve as another way to force the panel to stay flat during the processes such as lithography.

Fan out packaging usually involves picking and placing chips on a carrier, the poor adhesion between chip and carrier can lead to chip shifting as a result of molding and mold curing process, after which the chips may not be in its original position, and these chips cannot be properly patterned in the following lithography process. In short, chip shifting will directly translate to yield loss.

Possible solutions include using stronger adhesive to keep the chips in place during the entire process, or adopting CTE matched materials and optimized process parameter.

Chip shift compensation is another method to address this issue. Fig. 6 illustrates the concept of compensation by offsetting the die placement. Computer simulation is required to predict the overall trend of die shifting. The data can be applied to the die bonder to intentionally misplace the dies and allow the dies to shift back to the intended position after molding and curing process.

The adaptive mask alignment that comes with the stepper tool can perform a real time automated optical inspection and mask alignment correction. The stepper will adjust the chuck table to minimize the impact of misalignment.

There is another lithography technique known as Laser Direct Imaging, a more direct approach that reads the shifting amount of each chip at a time and generates a unique pattern with precision. The drawback of this technology is the minimal L/S feature and the low throughput for fine features.

The fan out technology in general can be categorized into four major types: chip first, chip last, chip middle and bump free. The following section will introduce these categories and discuss what applications they are suitable for.

“Chip first” fan out attaches the chip on the carrier and builds RDL after encapsulation. The active surface of the chip, with or without preformed bumps, could either be facing up or down.

If the chip is facing down, it will be followed by molding and detaching the panel from the carrier processes. The RDL will then be built on the molding compound surface. If the chip is facing up, it will require the grinding process on the molding surface to reveal the pads or bumps for the next RDL process. Fig. 8 shows the major process flow of chip first with facing up.

The chip first solution is suitable for application processor, baseband processor, ASIC, memory, and PMIC.

“Chip last” builds the RDL on the carrier first, and attaches the Cu-bumped chips later. The molding processes are performed after chip attachment. It provides the advantages of known good RDL because the RDL integrity could be checked before attaching the chips. It also reduces the issue of chip shift and RDL pattern misalignment. It is more possible to build finer traces because the RDL is built on a flat panel, which is different from the chip first process that builds RDL on mold surface.

Chip last fan out is ideal for devices with demand on high performance such as CPU, GPU, FPGA, or thermal sensitive devices.

“Chip middle” solution builds tall Cu pillars to connect package's top and bottom RDLs. This structure is ideal for package on package configuration. The upper RDL also allows high bandwidth connection between the lower chip and the upper package. Potential application for this solution includes stacking a memory package on top of an APU package where fast access to memory and low profiles are required. It is also suitable for RF module, sensor module, and other SiP applications.

“Bump less” eliminates the bumps on chip's active surface. After encapsulation, the RDL will be built on chip surface directly. It is a relatively lower cost solution than the chip first structure with bumps. It will be suitable for PMIC, audio, and PA devices.

For the coming 5G era, it is necessary to integrate the antenna into a RF IC package to meet the mmWave bandwidth requirement. Different structures to integrate an antenna into packages are developing. For example, the antenna can be integrated on substrate and package chips with the more matured flip chip process, or it can be built on another substrate or glass and then mount onto the package by PoP process. Fan out technology is another good method to build the antenna in package (AiP). Comparing to the antenna on substrate, the AiP with fan out solution has the benefits of lower signal loss due to shorter transmission routes. In addition, fan out process provides better line width/space control capability than the laminate substrate. Better dimensional control capability means consistent antenna performance that conforms to the design value. It is important for the high accuracy antenna design packages required for high frequency band in 5G telecommunication.

Panel level fan out is aimed to provide good solution for advanced SiP which involves packaging for identical chips, so called homogeneous integration, and packaging for different kind of chips, so called heterogeneous integration. Fig. 14 and Fig. 15 demonstrate some of the application cases of this technology.

There are many feasible applications that may apply the fan out technology. For example, FO_stack and FO_PoP for form factor and performance, FO_SiP that integrates passive and active chips, FO in package, FO_PoP with FI, embedded substrate, compartmental EMI shielding, and FO_sensor.

This paper has investigated the established packaging technologies of BGA SiP, 2.5D/3DIC, and wafer level fan out technology, as well as the emerging panel level fan out technology. The advantage and the challenges of panel level fan out packaging have been thoroughly investigated in this paper. The fine line fan out package can be a good platform to address the challenge of SoC, and it can integrate different functional chips into a package to act as the virtual SoC and will play an important role for “More than Moore” in the coming years.