In silicon capacitors, it is most important to increase the surface area of the surface forming the capacitor. In conventional silicon capacitors, trenches are generally formed in silicon wafer using reactive ion etching (RIE) method to expand their surface area. However, with this method, the depth of trenches that can be formed was limited. Furthermore, since RIE method processes silicon wafer only one by one, productivity is low. In this paper, Metal-assisted Chemical Etching (MacEtch) is proposed as a novel method of fabricating high-density silicon capacitors to solve the problems. We used gold formed by electroless plating as a catalyst and controlled them by forming conditions. As a result, vertical trenches greater than 100 μm depth and less than 1 μm width could be formed on a silicon wafer. The silicon wafer on which these trenches are formed has a surface area 100 times or more as compared with the case where there is no trench. We formed a dielectric film and electrodes on these trench surfaces. Consequently, we have realized a silicon capacitors with a capacitance density as high as 200 nF / mm2 or more.

The widespread use of mobile communication devices that aid ultra-high-speed communications and the progress in automotive electronics have led to the increasing demand for Multi-Layer Ceramic Capacitor (MLCC). Since MLCC mainly uses ferroelectrics such as BaO3Ti, issues such as low heat resistance, temperature and voltage dependence, and frequency dependence are associated with it. For example, the Application Processer (AP) of mobile phones, Power Management Integrated Circuit (PMIC) for stable operation of the Electronic Control Unit (ECU) on programmable module installation (PMI), and power supply for Intelligent Power Device (IPD) might require multiple capacitors in parallel with different frequency characteristics in order to lower the impedance in a wide range of frequencies.

On the other hand, a silicon (Si) capacitor, which is a type of Integrated Passive Device (IPD) has the potential to solve these problems. Fig. 1 shows the schematic of the cross-section of the Si capacitor structure. The Si capacitor is fabricated by forming a capacitor with a Metal-Insulator-Metal (MIM) structure on the surface of a Si substrate. By forming trench structures on the surface of a Si substrate and expanding the surface area, relatively large capacitance can be obtained by using not only ferroelectrics but also paraelectrics. Besides, Si capacitors have various features, such as low inductance, high heat resistance, and its relatively thin shape. In recent years, the Si capacitor has been garnering considerable attention as a capacitor that could replace MLCC [1]. However, the conventional Si capacitor uses dry etching of Si such as reactive-ion etching (RIE) to expand the surface area; thus, there are limits to the depth of the process as well as the capacity. Furthermore, there is a trade-off between withstand voltage and capacitance since the thickness of the dielectric film controls them. To obtain high capacitance and withstand voltage while maintaining the size of the dielectric in the planar direction, deep trenches with a high aspect ratio are needed. However, the dry etching process is a single wafer process and the cost of obtaining trench structures with a high aspect ratio is considerably high.

Fig. 1

Schematic structure of Si capacitor

Fig. 1

Schematic structure of Si capacitor

Close modal

We employed the Metal-assisted chemical Etching (MacEtch) method as a low-cost process of expanding the Si surface area to increase capacitance and withstand voltage of Si capacitor along with expanding the application area. In this study, we developed a novel fabrication process for Si capacitor by using MacEtch and present the corresponding result in this paper.

MacEtch is an anisotropic etching technique for Si by a wet process with noble metal catalysts. As shown in Figure 2, when noble metals such as gold (Au) and silver (Ag) are immersed in a mixed solution of hydrofluoric acid and hydrogen peroxide while in contact with Si, only the Si immediately below the noble metal catalyst is selectively dissolved. The noble metal catalyst moves downward, as shown in the figure, causing anisotropy [2].

Fig. 2

Schematic process flow of MacEtch.

Fig. 2

Schematic process flow of MacEtch.

Close modal

Conventional dry etching processes such as RIE, which are used for the anisotropic processing of Si, are single wafer methods that processes one wafer at a time. However, the MacEtch method could perform a batch process that simultaneously processes multiple wafers with high productivity, allowing for a substantial reduction in the processing cost. Furthermore, since the MacEtch method is an etching process with high anisotropy, supports processing with an aspect ratio higher than that by dry etching.

The MacEtch reaction mechanism that is currently being studied by several authors is considered to be an electrochemical corrosion mechanism that uses noble metals as the cathode and Si as the anode [28]. In other words, H2O2 is reduced on the surface of the noble metals, as shown in Equation (1); besides, holes (h+) that are formed through the decomposition of H2O2 oxidize Si at the contact boundary with the noble metals according to Equation (2). Further, the oxidized Si becomes soluble hexafluorosilicic acid (H2SiF6) through the reaction of HF and dissolves. As noble metal catalysts fall into the depression formed after the dissolution, the reaction is repeated, resulting in a progressive vertical etching process with high aspect ratio.

formula
formula

The required properties of catalysts derived from this mechanism include having a large surface area in contact with the etching solution in order to accelerate the reaction in Equation (1), supplying the etching solution for the reaction in Equation (2), not inhibiting the release of reaction products, and having a potential high enough to drive the corrosion current. Typical methods of catalyst formation include PVD methods such as vacuum evaporation and sputtering. The catalysts formed by such methods are in the form of a film; thus, a path must be formed for supplying the etching solution immediately below the catalysts and releasing the reaction products. The methods of forming this path include a method that uses lithography patterning, transfer of a self-assembled polymer template patterning and another method that yields an island-shaped porous film under vacuum evaporation conditions; however, these processes are complicated [3]. Furthermore, regarding two-dimensional film-shaped catalysts, the surface area is determined solely based on the pattern shape, and the film surface area cannot be further increased.

In this study, we employed a catalyst formation method based on the electroless plating method to solve this problem. By this method, the shape of deposition could be controlled using various conditions of the plating, including three-dimensional porous shapes. In this paper, we investigate the shape of deposition based on the amount of deposition and coverage, clarify the relationship between straightness of the trench process and them, and optimize that process.

3.1 The MacEtch process

An n-type Si wafer (100) with a resistivity of 10–20 Ω·cm was used as the substrate. A common positive photoresist was spin coated, exposed, and developed to form a Si-exposed pattern with width, length, and pitch of 1, 100, and 2 μm, respectively. After protecting the back side of the wafer using an acid-resistant tape, we immersed the wafer in a solution containing hydrofluoric acid and Au ions. Further, using displacement plating with plating conditions such as time and temperature as parameters, we formed an Au catalyst in the aforementioned Si-exposed area.

After removing the tape from the back side of the wafer with Au catalyst, the wafer was soaked in the etching solution (at 22°C)—a mixture of hydrofluoric acid and hydrogen peroxide—for the MacEtch process. For the MacEtch process, immersion time was used as a parameter. The mixture ratio of hydrofluoric acid and hydrogen peroxide impact the etching rate and shape [9]; however, in this experiment, to evaluate the impact of the catalyst surface area, we made the ratio HF/H2O2 constant at 7.5/2 mol/L. With the aforementioned process, the Si immediately below the Au catalyst is selectively and anisotropically etched, creating trenches of 2μm pitch on the Si wafer. The etching rate of MacEtch, process time, and straightness significantly impact the depth of the trench.

3.2 The evaluation methods for the MacEtch process

We evaluated the Au catalyst on the surface of Si with Field Emission - Scanning Electron Microscope (FE-SEM). In addition, we measured the amount of Au deposition using X-ray Fluorescence (XRF). Furthermore, using SEM, we observed the cross-section of the trenches formed in the Si by the MacEtch method to examine the straightness of the trenches formed by the MacEtch process and evaluated the completeness of trenches by using Nh/Nt, which is the ratio of the number of trenches on the top (Nt) and depth of h μm (Nh). When the straightness of trenches formed by the MacEtch method is poor, the adjacent trenches overlapped at a certain depth, thus reducing the number of trenches. Therefore, the value of Nh/Nt becomes less than 1; thus, the rectilinearity of the trench is simplified. When the depth h is large, and Nh/Nt is close to 1, the straightness of trenches is excellent.

3.3 Si capacitor formation

We used a Si wafer of ϕ = 6 inches to prepare a Si capacitor. Fig. 3 shows the flow of the main formation processes of the Si capacitor with trenches formed via the MacEtch method.

Fig. 3

Schematic process flow of a Si capacitor.

Fig. 3

Schematic process flow of a Si capacitor.

Close modal

First, using the MacEtch method shown in 3.1 and 3.2, we formed trench structures with width and pitch of 1 and 2 μm, respectively, on the Si wafer. The trench depth was in the range of 35–100 μm. As a post-MacEtch process, we removed the Au catalyst with aqua regia and cleaned using dilute hydrofluoric acid and nitric acid mixtures. Second, we doped the entire trenches with phosphorus to make the Si substrate n+. This was followed by formation of NO dielectric film using low pressure chemical vapor deposition (PECVD) silicon nitride 20 nm, thermal oxide <1 nm. Using LPCVD, we filled the trenches with doped polysilicon. Subsequently, we performed patterning of the polysilicon and the dielectric film. For patterning, after creating the resist pattern, we etched the polysilicon and dielectric film with Chemical Dry Etching (CDE) and Reactive Ion Etching (RIE), respectively. Further, we formed an Al-Si-Cu film by the sputtering method and performed patterning using RIE. Next, as a passivation film, we formed a tetraethyl orthosilicate (TEOS) film using the chemical vapor deposition (CVD) method; after patterning, we formed an opening above the Al–Si–Cu electrode.

Finally, we formed a Ni/Au film at this opening as an electrode pad by the electroless plating method. Two Si capacitor sizes were fabricated: 3216 and 1608, with external dimensions of 3.2 mm (L) × 1.6 mm (W) × 0.4 mm (H) and 1.6mm (L) × 0.8 mm (W) × 0.4mm (H), respectively.

3.4 Evaluation of the Si capacitor

We observed the cross-section of the prepared Si capacitor using an FE-SEM and measured the capacity by changing the temperature at a frequency of 1 kHz with the Agilent LCR meter 4294A.

4.1 The relationship between the catalyst formation process and straightness

Fig. 4 shows the relationship between the amount of Au catalyst deposit and Si etching rate. When making a comparison while the etching time and solution temperature were held constant, it was observed that the etching rate increases as the amount of Au deposit increases. This dependence indicates that the Au deposit morphology through the electroless plating is three-dimensional, and its surface area increases with the amount of Au deposit. Fig. 5 shows the SEM image of the Au catalyst under different conditions. Under a condition where the amount of catalyst deposit was high, the necking of particles occurred, thus creating a three-dimensional structure. Fig. 6 shows the cross-sectional SEM image of the trench formed by the MacEtch method using different amounts of Au catalyst deposit. When the amount of catalyst deposit was low, the rate was found to be relatively slow; the trench shape collapsed, forming a large number of Si needles. However, as the amount of catalyst increased, the shape of the trenches becomes stable, reducing the number of Si needles.

Fig. 4

The etch rate of MacEtch versus various Au deposit weights.

Fig. 4

The etch rate of MacEtch versus various Au deposit weights.

Close modal
Fig. 5

Cross-sectional SEM images of as-deposited Au particles.

Fig. 5

Cross-sectional SEM images of as-deposited Au particles.

Close modal
Fig. 6

Cross-sectional SEM images of trenches formed in various Au mass densities.

Fig. 6

Cross-sectional SEM images of trenches formed in various Au mass densities.

Close modal

Fig. 7 shows the relationship between the amount of deposit after the formation of catalyst and straightness, Nh/Nt, at a depth of 40 μm. When the amount of deposit was less than 50 μg/cm2, Nh/Nt was observed to be less than 40% and the straightness was poor. However, when the amount of deposit was in the range of 50–85 μg/cm2, Nh/Nt rose 100% and the individual trench was separated entirely from top to bottom. Further, when the amount of deposit exceeded 85 μg/cm2, Nh/Nt was observed to be less than 40%, deteriorating the straightness. Finally, when the amount of deposit was low, the distance between the catalyst particles increases; thus, the MacEtch occur independently between individual particles. Because the surface area of these particles was extremely small, the corrosion current between the catalyst and Si became considerably small; consequently, the etching rate decreased. Furthermore, there likely was the Coulomb attraction through silicon oxide between the catalyst and Si; however, the decrease in the corrosion current leads to decrease in the Coulomb attraction, which in turn decreases the straightness of the process. However, when the amount of catalyst deposit was too high, the catalyst approached the form of a film. Moreover, hydrogen gas generated during the dissolution of SiOx shown in Equation (2) caused the adhesion between Si and the catalyst to decrease; as the contact plane become misaligned, the process becomes warped, reducing the straightness. Furthermore, when the catalyst became a complete film, the etching solution supply and release of reaction products became inhibited; thus, the MacEtch did not progress.

Fig. 7

Relationship between straightness of trench and weight density of Au catalyst.

Fig. 7

Relationship between straightness of trench and weight density of Au catalyst.

Close modal

Based on the aforementioned experimental results, when using Au formed through electroless plating as a catalyst, to form deep trenches with a high degree of straightness while maintaining the completeness of the trench shape, the amount of Au deposit and coverage have optimal ranges. In the present experiment, the amount of deposit of 50–85 μg/cm2 was the optimum range. Fig. 8 shows the trench structure after the MacEtch when the Au catalyst formed under the optimal condition was used. We were able to form trenches with width, pitch, and depth of 1, 2, and 100 μm, respectively, and a high aspect ratio of 100, which is difficult to achieve even through dry etching.

Fig. 8

Cross-sectional SEM image of a trench formed by etching for 100 min in a solution of H2O2 (2 M) and HF (7.5 M) with Au as the catalyst.

Fig. 8

Cross-sectional SEM image of a trench formed by etching for 100 min in a solution of H2O2 (2 M) and HF (7.5 M) with Au as the catalyst.

Close modal

4.2 Characteristics of the Si capacitor

Fig. 9 shows the cross-section of the trench at each stage when fabricating a Si capacitor by using trenches formed by the MacEtch method. Fig. 9(a) shows the cross-section after the MacEtch with the aspect ratio of 40. Etching has progressed vertically, and there is a residual Au catalyst at the bottom of the trench. Fig. 9(b) shows the cross-section after removing the Au catalyst, wherein the Au catalyst at the bottom of the trench has been completely removed. Although there are residual Si needles in gaps of catalysts, these can be rinsed away using dilute hydrofluoric acid and nitric acid mixtures. Fig. 9(c) shows the cross-section when the dielectric film has formed after the removal of Si needles, and the trenches are filled with polysilicon. The interior of the trenches contain residual seams; however, there is no impact on the capacity properties. It should be noted that the polysilicon filling can improve this seam.

Fig. 9

Cross-sectional SEM images of MacEtch trenches: (a) After MacEtch, (b) After reduction of catalyst, (c) After dielectric and poly silicon deposited.

Fig. 9

Cross-sectional SEM images of MacEtch trenches: (a) After MacEtch, (b) After reduction of catalyst, (c) After dielectric and poly silicon deposited.

Close modal

Fig. 10(a) shows the appearance of the Si capacitor with high aspect ratio trenches on the Si wafer of ϕ = 6 inches. Fig. 10(b) shows the Si capacitor chip with a size of 3216 (3.2 mm×1.6 mm). Based on the result of the capacity measurement for the Si capacitor that used the trenches formed by the MacEtch process, we obtained up to 824 nF for the projection area of 3.9 mm2 of the polysilicon electrode observed from the top surface of the Si capacitor chip. The capacitance density at this case reaches 210 nF/mm2.

Fig. 10

The images of silicon capacitor : (a) Whole of wafer, (b) Chip.

Fig. 10

The images of silicon capacitor : (a) Whole of wafer, (b) Chip.

Close modal

Fig. 11 shows the comparison for the temperature dependence of capacitance of the prepared Si capacitor and MLCC. The Si capacitor was 400 nF, and the MLCC was 470 nF B/X-5R Series (1608 in size). While the MLCC presented changes in the capacity of 50% or more at 150°C or more, the Si capacitor presented small changes of 8% or less at 200°C.

Fig. 11

Capacitance change ratio dependence on temperature.

Fig. 11

Capacitance change ratio dependence on temperature.

Close modal

By regulating the shape of catalyst in the MacEtch, vertical etching processing was improved, and a trench structure with the width and depth of 1 and 100 μm, respectively, i.e. with the aspect ratio of 100 was realized. Furthermore, by forming this trench on the surface of the Si wafer and fabricating a capacitor structure on the surface with an expanded surface area, we developed a Si capacitor with a capacitance of 200 nF/mm2 or more. This Si capacitor is expected to be produced at a low cost through the use of the MacEtch process with high productivity. Based on the present results, the developed Si capacitor may able to substitute the MLCC for applications that require high stability and heat resistance.

[1]
F.
Murray
,
F.
LeCornce
,
S.
Bardy
,
C.
Bunel
,
Jan F.C.
Vehoeven
,
F.C.M..
van den Heuvel
,
J.H.
Klootwijk
,
F.
Roozeboom
,
“Silicon Based System-in-Package : a new technology platform supported by very high quality passives and system level design tools,”
IEEE-SiRF
2007
.
[2]
X.
Li
,
“Metal-assisted chemical etching in HF/H2O2 produces porous silicon,”
Appl. Phys. Lett
.,
vol. 77
,
p
.
2572
,
2000
.
[3]
Z.
Huang
,
“Metal-Assisted Chemical Etching of Silicon: A Review,”
Adv. Mater
.,
vol. 23
,
pp
.
285
308
,
2011
.
[4]
K.
Peng
,
“Fabrication of Single-Crystalline Silicon Nanowires by Scratching a Silicon Surface with Catalytic Metal Particles,”
Adv. Funct. Mater
.,
vol. 16
,
pp
.
387
394
,
2006
.
[5]
L.
Li
,
“Uniform Vertical Trench Etching on Silicon with High Aspect Ratio by Metal-Assisted Chemical Etching Using Nanoporous Catalysts,”
ACS Appl. Mater. Interfaces
,
vol. 6
,
pp
.
575
584
,
2014
.
[6]
P.
Lianto
,
“Vertical etching with isolated catalysts in metal-assisted chemical etching of silicon,”
Nanoscale
,
vol. 4
,
pp
.
7532
7539
,
2012
.
[7]
C.
Chartier
,
“Metal-assisted chemical etching of silicon in HF–H2O2,”
Electrochimica Acta
,
vol. 53
,
p
.
5509
,
2008
.
[8]
K.
Peng
,
“Motility of Metal Nanoparticles in Silicon and Induced Anisotropic Silicon Etching,”
Adv. Funct. Mater
.,
vol. 18
,
pp
.
3026
3035
,
2008
.
[9]
Y.
Asano
,
K.
Matsuo
,
H.
Ito
,
K.
Higuchi
,
K.
Shimokawa
, and
T.
Sato
,
“A novel wafer dicing method using metal-assisted chemical etching, ”
in
Proc. 65th Electron. Compon. Technol. Conf. (ECTC)
,
San Diego, CA, USA
,
May 2015
,
pp
.
853
858
.