Volume 2012 Issue 1 | International Symposium on Microelectronics

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Predicting the Reliability of Zero-Level TSVs

Greg Caswell; Craig Hillman

An Overview - Temporary Wafer Bonding / Debonding for 2.5D and 3D Technologies

Rajen Chanchani

Optimizing Product Cost with Supply Chain Cost Modeling

Chet Palesko; Alan Palesko

3D Integration of Wide IO Memory Cube Stacking to 28 nm Logic Chip with High Density TSV through a Fabless Supplier Chain

S.Q. Gu; D.W. King; V. Ramachandran; B. Henderson; U. Ray; M. Nowak

Understanding and Controlling Cu Protrusions in 3D TSV Processing

Seth Kruger; Klaus Hummler; Robert Geer; Kathleen Dunn; Colin McDonough; Aaron Cordes; Jack Enloe; Brian Sapp; Iqbal Ali; Stefan Pieper; Sitaram Arkalgud; Thomas Murray

A Novel Wafer-Level Double Side Packaging and Its Microwave Performance

Xiao Chen; Jiajie Tang; Gaowei Xu; Le Luo

High-Reliability Component Attachment Process for <5μm Placement Accuracy

Donald J. Beck; Zeger Bok; Daniel Martinez

Getters and Design to Reliability: A Tool For Lifetime Assurance

Richard C. Kullberg; Bradley L. Phillip

Advanced Manufacturing Methods for Brazing High-Reliability Electronic Packages

Iris Labadie

Reliability analysis of low-Ag BGA solder joints using four failure criteria

Erin Kimura; Jianbiao Pan, Ph.D.

NiV Stress Control Utilizing PVD with an Ar / N₂ Gas Mixture

G. Seryogin; S. Golovato; S. Smith; K. Williams; N. Limburn; A. Winn; G. Mundada; G. Adema

Planarization of Deep Structures Using Self-Leveling Materials

Dongshun Bai; Michelle Fowler; Curtis Planje; Xie Shao

Effects of the Impurities on the Embrittlement Phenomena of Electroplated Nickel Films

Yoonchul Sohn; Minjong Bae; Inyong Song; Sangeui Lee; Dongouk Kim; Kunmo Chu; Dongun Kim; Sunghoon Park; Hajin Kim; Intaek Han

CO₂ Technology Transforms Manufacturing

David Jackson

Mixed Attachment Technology Studies in RF & Optoelectronic Packages Requiring High Accuracy Placement

Daniel D. Evans; Zeger Bok

XTRONIC®: Enabler of Improved Performance with Reduced Precious Metal Usage in Microelectronics

D.M. Baskin; B.C. Muñoz; J.S. Sylvester; J.P. Cahalen; A.C. Lund

Pb-free PBGA Design Points to Improve Handling Robustness

Isabel de Sousa; Brian Roggeman; Oswaldo Chacon; Niki Spencer; Mamoru Ueno

HIGH RELIABILITY HIGH MELTING LEAD-FREE MIXED BIAGX SOLDER PASTE SYSTEM

HongWen Zhang; Ning-Cheng Lee

Effects of Extended Dwell Time on Thermal Fatigue Life of Ceramic Chip Resistors

Elviz George; Michael Osterman; Michael Pecht; Richard Coyle

Material Analysis of Lead Free Solder Deposited by Electrochemical Deposition

Tom Ritzdorf; Sam Lee; Ian Drucker

Smart and Quick Dk, Df Extraction Flow of Halogen-free and Lead-free Materials under Different Temperatures

Chang-Chih Liu; Cheng-Hua Tsai; Wei-Ting Chen; Chang-Sheng Cheng; Li-Chi Chang

Reliability Study of Reference Semiconductor Encapsulation Materials for Biocompatible Packaging

Karl Malachowski; Karen Qian; Maaike Op de Beeck; Rita Verbeeck; George Bryce; Harold Dekkers; Deniz S. Tezcan

Assembly and Packaging of a Wireless, Chronically-Implantable Neural Prosthetic Device

Kedar G. Shah; A. Tooker; V. Tolosa; T. DeLima; W. Benett; S. Felix; H. Sheth; S. Pannu

Epidermal electronics for health and fitness monitoring

Conor Rafferty; Mitul Dalal; Dan Davis; Brian Elolampi; Yung-Yu Hsu; Stephen Lee; Lauren Klinker; Briana Morey

Laminate Materials for Microfluidic PCBs

Sarkis Babikian; Brian Soriano; G.P. Li; Mark Bachman

Process integration solution for damage-free bevel for deep Si etch applications

Bivragh Majeed; Nina Tutunjyan; Paolo Fiorini; Deniz. S. Tezcan

Parylene as Thin Flexible 3-D Packaging Enabler for Biomedical Implants

Jimin Maeng; Dohyuk Ha; William J. Chappell; Pedro P. Irazoqui

Miniaturization of Electronic Substrates for Medical Device Applications

Frank D. Egitto; Rabindra N. Das; Glen E. Thomas; Susan Bagen

Realisation of High Temperature Electronics Packaging Technology for Sensor Conditioning and Processing Applications

S T Riches; C Johnston; A Lui

SYSTEMATIC FEEDBACK LOOP FOR SILICON DIE PICK&PLACE PROCESS IN RECONSTITUTED FAN-OUT EWLB WAFERS IN HIGH VOLUME PRODUCTION

Alberto Martins; Nelson Pinho; Harald Meixner

European R&D Trends in wire bonding technologies

M. Schneider-Ramelow; J.-M. Göhre; U. Geißler; S. Schmitz; K.-D. Lang

Biocompatible encapsulation and interconnection technology for implantable electronic devices

Maaike Op de Beeck; John O'Callaghan; Karen Qian; Bishoy M. Morcos; Aleksandar Radisic; Karl Malachowski; M. F. Amira; Chris Van Hoof

Packaging of High Power UV-LED Modules on Ceramic and Aluminum Substrates

Marc Schneider; Benjamin Leyrer; Christian Herbold; Stefan Maikowske

Through-Silicon-Via (TSV) for silicon package: ″via-bridge″ approach

Y. Lamy; S. Joblot; C. Ferrandon; J.F. Carpentier; G. Simon

High Frequency Signal Propagation in Through Silicon Vias

Srinidhi Raghavan Narasimhan; A. Ege Engin

Through Silicon Via (TSV) Technology Creates Electro-Optical Interfaces

Phil Marcoux

Quality and Reliability of 3D High-Performance Heterogeneous Integration through Die Stacking

Bahareh Banijamali; Liam Madden; Suresh Ramalingam; Ephrem Wu

Enabling the 2.5D Integration

John Y. Xie, Ph.D.; Hong Shi, Ph.D.; Yuan Li, Ph.D.; Zhe Li; Arif Rahman, Ph.D.; Karthik Chandrasekar, Ph.D; Deepa Ratakonda; Manish Deo; Kaushik Chanda; Vincent Hool; MJ Lee; Nagesh Vodrahalli, Ph.D.; Dale Ibbotson, Ph.D.; Tarun Verma

DESIGN AND PROCESS OPTIMIZATION OF THROUGH SILICON VIA INTERPOSER FOR 3D-IC INTEGRATION

Pejman Monajemi; Michael Newman; Cyprian Uzoh; Charles Woychik; Terrence Caskey

Process challenges in 0-level packaging using 100μm-thin chip capping with TSV

Nga P. Pham; Vladimir Cherman; Nina Tutunjyan; Lieve Teugels; Deniz S. Tezcan; Harrie A.C. Tilmans

A Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Reference, Legacy, & Premium Backplane Channels

Chad Morgan; Adam Healey

Measurement-based Signal Quality Test of High-speed TSV Channel

Heegon Kim; Jonghyun Cho; Daniel H. Jung; Jonghoon J. Kim; Joungho Kim; Jun So Pak; Kwang-Seong Choi; Hyun-Cheol Bae

IC Package Optimization Targeting Multiple Form Factors

John Park

Impact of etch factor on characteristic impedance, crosstalk and board density

Abdelghani Renbi; Arash Risseh; Rikard Qvarnström; Jerker Delsing

Propagation Delay Analysis in 3D Stacked Memory using Novel MOS Depletion Layer Modeling Approach for Through Silicon Via

Kaushal Kannan; Sarma G. Harihara; Sukeshwar Kannan

Thin-Film Signal and Power Redistribution Layers Based on AL-X and Cu

John Bailey; Alexander Pfeiffenberger; Charles Ellis; Mike Palmer; Tamara Issac-Smith; Michael Hamilton

Meander Delay Compensation in High-Speed Digital Multilayer Packages

Robert Frye; Kai Liu

The Application of PEEK to Implantable Electronic Devices Packaging: Water Permeation Calculation Method and Maximum Lifetime with Desiccant

Nathaniel Dahan; Nick Donaldson; Stephen Taylor; Nuno Sereno

Precision Jetting of Glob Top Materials – a methodology for process optimization

K.-F. Becker; M. Koch; J. Bauer; T. Braun; R. Aschenbrenner; M. Schneider-Ramelow; K.-D. Lang

Simulation and Experiment of Molded Underfill Voids

MyoungSu Chae; Eric Ouyang; JaeHan Chung; DokOk Yu; SeonMo Gu; Gwang Kim; Billy Ahn

Highly Conducting Carbon Nanotube Composite for Light-Weight Electric Heating Unit Applications

Kunmo Chu; Sunghoon Park; Sangeui Lee; Dongouk Kim; Yoonchul Sohn; Dongun Kim; Minjong Bae; Hajin Kim; Intaek Han

Multi-functional carbon nanotube composites with super-hydrophobic properties

Sunghoon Park; Eunhyoung Cho; Paul Thielemann; Jinseung Sohn; Kunmo Chu; Sunghee Lee; Dongouk Kim; Byunghoon Kim

Managing Voids in Underfill Process with 5-micron Gap Under Large Die

Hanzhuang Liang; Nordson Asymtek

Use of Wire Bonding to Study Bond Pad Damage from Wafer Probe

Stevan Hunter; Jonathan L. Clark; Darin Hornberger; Lance Rubio

Pd-coated Cu Wire Bonding Reliability Requirement for Device Design, Process Optimization and Testing

Inderjit Singh; Shin Low; Syu Fu Song; Chen Shih Jung; Lin Ming San; Ivy Qin; Cuong Huynh; Horst Clauberg; Son Truong Nguyen; Bob Chylak; Hui Xu; Viola L. Acoff

Wedge Bonding RF and Microwave Devices

Joe Bubel; Lee Levine

Gold Ball Wire Bonding with Heated Tool for Automotive Microelectronics

David J Rasmussen

Glass-Insulated Bonding Wire Scales to Support advances in Miniaturization

Dominik Stephan

Demonstration of Inkjet Printed Nanoparticle-based Inks for Solder Bump Replacement

Jacob Sadie; Steven Volkman; Vivek Subramanian

A Novel Packaging Concept for Electronics in Textile UHF Antennas

Christian Boehme; René Vieroth; Mervi Hirvonen

Comparison between Single & Multi Beam Laser Grooving of Low-K layers

Jeroen van Borkulo; Rene Hendriks; Peter Dijkstra

Electrical and Mechanical Performance of Quilt Packaging with Solder Paste by Pin Transfer

Quanling Zheng; M. Ashraf Khan; Alfred M. Kriman; Gary H. Bernstein

Advanced Stepper Through-Silicon Alignment (TSA) Evaluation and Overlay of Distorted Bonded Wafer Stacks

Doug Shelton; C.Y. (Charles) Wang

Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

Yasumitsu Orii; Kazushige Toriyama; Sayuri Kohara; Hirokazu Noma; Keishi Okamoto; Keisuke Uenishi

Planar Power Inductor with Magnetic Film for Embedded LSI Package

Tomoharu Fujii; Kazutaka Kobayashi; Hiroshi Shimizu; Shinji Nakazawa; Toshiro Sato; Fumihiro Sato; Hiroki Kobayashi

Investigation of electrical performance and mechanical reliability of device embedded power module

Masaya Tanaka; Keisuke Sawada; Toru Serizawa; Shuji Sagara

New Flip-Chip Interconnect Technology for High Performance and High Reliability Applications

Eiji Yamaguchi; Mutsuo Tsuji; Nozomi Shimoishizaka; Takahiro Nakano; Katsunori Hirata

Control of Package Warpage by Package Substrate Design for Low Profile Package-on-Package Structure

Takeshi Furusawa; Naomi Kawamura; Toshiki Furutani; Takashi Kariya

Low Temperature Hybrid Bonding of Organic/Inorganic Substrates at Atmospheric Pressure

Akitsu Shigetou

Electromigration Reliability of Glass Ceramic Multilayer Substrate with Various Surface Finishes

Hiroshi Matsumoto; Akira Wakazaki; Shingo Sato; Takashi Okunosono; Chihiro Makihara

Evaluating the Impact of Dwell Time on Solder Interconnect Durability under Bending Loads

Sandeep Menon; Michael Osterman; Michael Pecht

Manual Assembly of 400um Bumped-Die GaN Power Semiconductor Devices

Stephan W. Henning; Luke Jenkins; Sidni Hale; Christopher G. Wilson; John Tennant; Justin Moses; Mike Palmer; Robert N. Dean

Design and Robustness of Quilt Packaging Superconnect

M. Ashraf Khan; Jason M. Kulick; Alfred M. Kriman; Gary H. Bernstein

BGA Solder Life Prediction under Combined Power and Temperature Cycling Condition

Fei Chai; Michael Osterman; Michael Pecht

Small Pitch Micro-Bumping and Experimental Investigation for Under Filling 3D Stacking

Antonio La Manna; K. J. Rebibis; J. De Vos; L. Bogaerts; C. Gerets; E. Beyne

Challenges in 3D Inspection of Micro Bumps Used in 3D Packaging

Reza Asgari

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

Fuliang Le; S. W. Ricky Lee; Jingshen Wu; Matthew M. F. Yuen

Use of 3D Packaging Technology for Satellite Active Antennas Front-ends

B. Bonnet; R. Chiniard; H. Legay; D. Nevo; P. Monfraix; O. Vendier; P. Couderc; J.-L. Cazaux

Package-Interposer-Package (PIP): A Breakthrough Package-on-Package (PoP) Technology for 3D-Integration

Rabindra N. Das; Frank D. Egitto; Barry Bonitz; Erich Kopp; Mark D. Poliks; Voya R. Markovich

Temporary Bonding and Debonding - An Overview of Today's Materials and Methods

RF/Microwave Die Attach of Gallium Nitride Devices Achieving Less Than 1% Voiding in a Flux-Free Environment

Pierino I Zappella; Paul W Barnes; David Muhs; Bruce Wilson

A Numerical Study of Single Phase Dielectric Fluid Immersion Cooling of Multichip Modules

Roy W. Knight; Seth Fincher; Sushil H. Bhavnani; Daniel K. Harris; R. Wayne Johnson

Obsolescence Management & the Impact on Reliability

Cheryl Tulkoff; Greg Caswell

Characterization of silicate sensors on Low Temperature Cofire Ceramic (LTCC) substrates using DSC and XRD techniques

Mary Ruales; Kinzy Jones

A Ceramic Tubular Probe For Online Substance Concentration Measurement, Manufactured By Ceramic Injection Molding

Matthias Hartmann; Bertram Schmidt

Development of High-Dielectric-Strength Ceramic Film Capacitors for Advanced Power Electronics

Beihai Ma; Manoj Narayanan; Shanshan Liu; Sheng Tong; U. (Balu) Balachandran

Comparison of Silver vs. Gold Systems in High-Q FTTF LTCC Inductors

Matthew J. Clewell; William B. Kuhn

Evaluation of Exothermic Reactions in Cofired Platinum /Alumina Microsystems

Ali Karbasi; W. Kinzy Jones

Radiation Mechanisms and Electromagnetic Interference in Ceramic Electronic Packages

Jerry Aguirre; Marcos Vargas; Paul Garland

Copper Wire Bonding: R&D to High Volume Manufacturing

Bob Chylak; Horst Clauberg; John Foley; Ivy Qin

How to Deal with Resonances in Wirebonding

Josef Sedlmair; Uwe Nacke

Response of Long Sculpted Wire Bonds to Vibrational Excitation

Thomas F. Marinis; Joseph W. Soucy

A Process For Treating Woven Glass Cloth

Dylan Boday; Michael Haag; Joe Kuczynski; Markus Schmidt; Michael Wahl

Novel ESD Protection Scheme for Testing High Voltage LDMOS

Sukeshwar Kannan; Bruce Kim; Friedrich Taenzler; Richard Antley; Ken Moushegian

Making New With Old

Nick Renaud-Bezot; Mark Beesley

Photostabilization of i-line Photoresist and ARC Layer

Zeliha YILMAZ; Murat PAK; Sema İMRAHORILYAS; Aylin ERSOY

A Novel OPC Technique for 2D Critical Dimension Optimization of Sub-micron Patterns using an Experimental Methodology

Murat Pak; Zeliha Yilmaz; Aylin Ersoy

ULTRA THIN CHIPS STACKING ON TSV SILICON INTERPOSER USING BACK-TO-FACE TECHNOLOGY

G. Parès; F. Schnegg; A. Attard; D. Cruau; F. De Crecy; A. N'hari; R. Anciant; G. Klug; H. Luesebrink; K. Martinschitz; C. Karoui; G. Simon

Method to measure wafer stiffness in Fan-Out Wafer Level Package

Jorge Teixeira; Mário Ribeiro

Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging

Stephen Kenny; Kai Matejat; Sven Lamprecht; Olivier Mann

Stacking Aspects in the View of Scaling.

Joeri De Vos; Antonio La Manna; Robert Daily; Kenneth June Rebibis; Eric Beyne

Aerosol-Jet Printing for Functionalization of Prototyping Materials for Electronic Applications

Johannes Hörber; Christian Goth; Jörg Franke

Formulation of percolating thermal underfills using hierarchical self-assembly of micro- and nanoparticles by centrifugal forces and capillary bridging

Thomas Brunschwiler; Gerd Schlottig; Songbo Ni; Yu Liu; Javier V. Goicochea; Jonas Zürcher; Heiko Wolf

Glass Wafers as Support Carriers for Wafer Thinning Processes

Aric Shorey; John Keech; Windsor Thomas

Development of Through Glass Vias (TGV) for 3D-IC Integration

Aric Shorey; Scott Pollard; John Keech

Characterization of Interconnects and RF Components on Glass Interposers

Ivan Ndip; Michael Töpper; Kai Löbbicke; Abdurrahman Öz; Stephan Guttowski; Herbert Reichl; Klaus-Dieter Lang

Cost effective 3D Glass Microfabrication for Advanced Packaging Applications

Jeb H. Flemming; Kevin Dunn; James Gouker; Carrie Schmidt; Roger Cook

Formation of Through-Glass-Via (TGV) by Photo-Chemical Etching with High Selectivity

Zingway Pei; Jui-Po Sun; Hsin-Chen Lai; Pei-Jer Tzeng; Cha-Hsin Lin; Tzu-Kun Ku; Ming-Jer Kao

A Wafer-level System Integration Technology Incorporates Heterogeneous Devices

Hiroshi Yamada; Yutaka Onozuka; Atsuko Iida; Kazuhiko Itaya; Hideyuki Funaki

Isothermal Aging Effects on the Thermal reliability Performance of Lead-Free Solder Joints

Jiawei Zhang; Zhou Hai; Sivasubramanian Thirugnanasambandam; John L. Evans; M. J. Bozack

Thermal Characterization and Simulation of a fcBGA-H device

Eric Ouyang; Weikun He; YongHyuk Jeong; MyoungSu Chae; SeonMo Gu; Gwang Kim; Billy Ahn

Mechanical Stress Analysis and Evaluation of Hybrid Land Grid Array Attached Large Form Factor Organic Modules

John Torok; Shawn Canfield; Yuet-Ying Yu; Jiantao Zheng

Package Reliability Monitored Drop Shock and Temperature Cycling Testing Progression and Advantages

Michael Ferrara

Superior Drop Test Performance of BGA Assembly Using SAC105Ti Solder Sphere

Weiping Liu; Ning-Cheng Lee; Simin Bagheri; Polina Snugovesky; Jason Bragg; Russell Brush; Blake Harper

Solution for HVM TSV Etch Process

Rajiv Roy; Matt Wilson

Accurate Prediction of Thermal Resistance of FET by Detailed Modeling of Heat Generation and Backend Stackup

Qun Wan; Don Willis; Daniel Jin

Design Optimization of Micro-channel Heat Exchanger embedded in LTCC

Aparna Aravelli; Singiresu S. Rao; Hari K. Adluru

Thermal Power of Mobile Application Processor

Heung Kyu Kwon; Jugnwook Hwang; Hyunkwon Chung; Munsik Kang; Hyun Duk Cho; Young Min Kim

Stacked Chip Thermal Model Validation using Thermal Test Chips

Thomas Tarter; Bernie Siegal

Influence of thermal ageing on void content and shear strength for selected lead free solder die-attach

K. C. Otiaba; N. Raju; R. S. Bhatti; S. Mallik; P.K. Bernasko

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

Rainer Dohle; Stefan Härter; Andreas Wirth; Jörg Goßler; Marek Gorywoda; Andreas Reinhardt; Jörg Franke

Optimization of Ag Composition in Cu Pillar Bumps with Sn-xAg Solders

Moon Gi Cho; Hwan Sik Lim; Sun Hee Park; Yong Hwan Kwon; Jaesik Chung; Jinho Choi; Eun-Chul Ahn

Assessment of XRF Technique as a Method to Measure Percent Ag in SnAg Solders for Flip Chip Applications

Jennifer D Schuler; Chia-Hsin Shih; Charles L Arvin; KyungMoon Kim; Eric Perfecto

The Distribution and Transport of Alpha Activity in Tin

Brett M. Clark

Development of Silver Nanoparticle Ink for Printed Electronics

Yiliang Wu; Ping Liu; Tony Wigglesworth

High Yield Embedding of 30μm Thin Chips in a Flexible PCB using a Photopatternable Polyimide based Ultra-Thin Chip Package (UTCP)

T. Sterken; M. Op de Beeck; F. Vermeiren; T. Torfs; L. Wang; S. Priyabadini; K. Dhaenens; D. Cuypers; J. Vanfleteren

Additive Manufacturing of Fine Lines and Embedded Electronics for use in Chip Carriers and Microelectronic Systems

Scott Lauer; Whitten Little; Pier Benci; Tim Schmitt; John Mazurowski

Rediscovering Multilayer Rigid-Flex with Z-interconnect Technology

Rabindra N. Das; John M. Lauffer; Frank D. Egitto; Mark D. Poliks; Voya R. Markovich

Development of Printed Power Packaging for a High Voltage SiC Module

Haotao KE; Douglas C Hopkins

Heterogeneous Process Development for Electronic Device Packaging with Direct Printed Additive Manufacturing

R. X. Rodriguez; K. Church; X. Chen

Study of Warpage and Mechanical Stress of 2.5D Package Interposers during Chip and Interposer Mount Process

Takashi Hisada; Yasuharu Yamada; Junko Asai; Toyohiro Aoki

Handling technology for 0.075-square mm powder IC chip

Hideyuki Noda

Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator Incorporating High Density TSVs and Interconnects

Ken Miyairi; Masahiro Sunohara; Jean Charbonnier; Myriam Assous; Jean-Philippe Bally; Robert Cuchet; Helene Feldis; Kei Murayama; Mitsuhiro Aizawa; Gilles Simon; Mitsutoshi Higashi

New Build-up Insulation Material Based on Cyclo-Olefin Polymer for High-Performance IC Packages

Yohei Tateishi; Makoto Fujimura; Takashi Iga; Toshihiko Jimbo

Scallop Free Si Etching and Low Cost Integration Technologies for 2.5D Si Interposer.

Yasuhiro Morikawa; Takahide Murayama; Toshiyuki Sakuishi; Toshiyuki Nakamura; Takashi Kurimoto; Yuu Nakamuta; Isao Kimura; Koukou Suu

Thermomechanical Design for Fine Pitch 3D-IC Packages

Akihiro Horibe; Sayuri Kohara; Kuniaki Sueoka; Keiji Matsumoto; Yasumitsu Orii; Fumiaki Yamada

Thinner and Miniaturization Embedded Device Package, MCeP, for PoP and Module Application

Kouichi Tanaka; Nobuyuki Kurashima; Hajime Iizuka; Kiyoshi Ooi; Yoshihiro Machida; Satoshi Shiraki; Tetsuya Koyama

Electromigration Performance of Fine-Pitch Copper Pillar Interconnections

Ahmer Syed; Christopher J. Berry; Karthikeyan Dhandapani; Patrick Thompson; Seung-Hyun Chae

Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation across the Chip & Package Domains in 3D IC's

Mark Nakamoto; Karthikeyan Dhandapani; Wei Zhao; Ahmer Syed; Wei Lin; Riko Radojcic

PoP Package Warpage Contributors' Characterization and Impact Analysis

Shengmin Wen

Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application

Sheng-Tsai Wu; John H. Lau; Heng-Chieh Chien; Yu-Lin Chao; Ra-Min Tain; Li Li; Peng Su; Jie Xue; Mark Brillhart

Solder Joint Ductility

Robert Darveaux; Michael Johnson; Corey Reichman

3D Electromagnetic Modeling of Through Silicon Vias and Interposers in Electronic Packaging

Darryl Kostka; Antonio Ciccomancini Scogna

A Practical Approach to Analyze Copper Surface Roughness Effects with Applications to Stripline Structures

Xichen Guo; Ji Chen; David R. Jackson; Marina Y. Koledintseva; James Drewniak; Christopher Pan

Influence of Different Packaging and Footprint Technique for Microwave Absorptive Bessel Filter's Performance

Akhlaq Rahman; Jim Norman

Qualification of Polyimide Based Coverlays for 900 MHz and 2.40 GHz Microstrip Antenna Applications

Deepukumar Nair; Glenn Oliver; Jim Parisi

Virtual Ground Fence: A Simple Method for Protection against High Frequency Simultaneous Switching Noise

Jesse Bowman; A. Ege Engin

Dicing Development for low-k Copper Wafers using Nickel-Palladium-Gold Bond Pads for Automotive Application

Tu Anh Tran; Varughese Mathew; Wen Shi Koh; K. Y. Yow; Y. K. Au

Characterization of Over Pad Metallization (OPM) for High Temperature Reliability

Varughese Mathew; Tu Anh Tran

Packaging of High Frequency, High Temperature Silicon Carbide (SiC) Multichip Power Module (MCPM) Bi-directional Battery Chargers for Next Generation Hybrid Electric Vehicles

Z. Cole; B. Passmore; B. Whitaker; A. Barkley; T. McNutt; A.B. Lostetter

Thin-film High Voltage Capacitors for Hybrid Electric Vehicle Inverter Applications

M. Ray Fairchild; Carl W. Berlin; D.H.R. Sarma, Ph.D.; Ralph S. Taylor; Han S. Lee; Steven E. Staller

High Temperature Packaging for SiC Power Transistors

K. Brinkfeldt; T. Åklint; C. Sandberg; P. Johander; D. Andersson

Novel ultra-compact quad-band System-in-Package (SiP) module with IC embedded in substrate based on SESUB technology.

V. Sieroshtan; G. Sevskiy; P. Komakha; O. Aleksieiev; A. Burygin; O. Chayka; O. Ruban; M. Shevelov; K. Kato; A. Horibe; H. Fujioka; K. Ruffing; P. Heide; M. Vossiek

Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)

Ilyas Mohammed

Embedded Die Substrates for Power Applications

Bernd K Appelt; Bruce Su; Uno Yen; Kay Essig

Thin Substrates Bursting into the Market

Bernd K Appelt; Bruce Su; Dora Lee; Kidd Lee; Uno Yen

Pushing the 3rd Dimension – Floppy Wafers, Die and Packages? Stress Induced Chip Package Interactions on Thin Mobile Devices

Mark Nakamoto; Wei Zhao; Riko Radojcic

Thin PoP: Warpage Control for Thinner PoP Package in Mobile Applications

Yuka Tamadate; Seiji Sato; Hitomi Imai; Kota Takeda; Takeshi Meguro; Takashi Ozawa

Highly Flexible Die Attach Adhesives for MEMS packages

Tobias Königer

A Low Firing Temperature Copper Conductor for use on an Aluminum Metal Compatible Dielectric in LED Thermal Substrate Applications

Samson Shahbazi; Steve Grabey; Ryan Persons

Hardware Design for Multiple Gas Detection System Using Zeolite Coated with Nile Red

Son Nguyen; Z. Joan Delalic; David M. Kargbo; Joel B. Sheffield

Development of Synergistic Opto-Electronic Sensing Platform based on Zinc Oxide Semiconducting Nanostructures

Anurag Gupta; Bruce C. Kim; Mitchell Spryn; Eugene Edwards; Christina Brantley; Paul Ruffin

ACES characterization of damping in micro-beam resonators

Jason Parker; Xiuping Chen; Vu Nguyen; Ryszard J. Pryputniewicz

Large Size Silicon Interposer and 3D IC Integration for System-in-Packaging (SiP)

John Lau; Pei-Jer Tzeng; Chau-Jie Zhan; Ching-Kuan Lee; Ming-Ji Dai; Jui-Chin Chen; Yu-Chen Hsin; Shang-Chun Chen; Chien-Ying Wu; Li Li; Peng Su; Jie Xue; Mark Brillhart

GHz High Frequency TSV for 2.5D IC Packaging

Chi-Han Chen; Kuan-Chung Lu; Chang-Ying Hung; Pao-Nan Lee; Meng-Jen Wang; Chih-Pin Hung; Ho-Ming Tong; Tzyy-Sheng Horng

Electrical Performance of Through-Silicon Vias (TSVs) for High-Frequency 3D IC Integration Applications

Jui-Feng Hung; John H. Lau; Peng-Shu Chen; Shih-Hsien Wu; Sheng-Che Hung; Shinn-Juh Lai; Ming-Lin Li; Shyh-Shyuan Sheu; Zhe-Hui Lin; Chih-Sheng Lin; Wei-Chung Lo; Ming-Jer Kao