Skip Nav Destination
Issues
IMAPS 2017
Ultra-fine Line Multi-Redistribution Layers with 10 μm Pitch Micro-Vias for Wafer Level and Panel Level Packaging realized by an innovative Excimer Laser Dual Damascene Process
Robert Gernhardt; Friedrich Müller; Markus Woehrmann; Habib Hichri; Karin Hauck; Michael Toepper; Markus Arendt; Klaus-Dieter Lang
A Generic Strategy to Assess and Mitigate Chip Package Interaction Risk Factors for Semiconductor Devices with Ultra-low k Dielectric Materials in Back End of Line
Frank Kuechenmeister; Dirk Breuer; Holm Geisler; Christian Klewer; Bjoern Boehme; Kashi Vishwanath Machani; Michael Hecker; Christian Goetze; Jae Kyu Cho; Himani Kamineni; Jens Paul; Michael Thiele
Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)
John Lau; Ming Li; Nelson Fan; Eric Kuah; Zhang Li; Kim Hwee Tan; Tony Chen; Iris Xu; Margie Li; Y. M. Cheung; Wu Kai; Ji Hao; Rozalia Beica; Tom Taylor; CT Ko; Henry Yang; YH Chen; Sze Pei Lim; NC Lee; Jiang Ran; Koh Sau Wee; Qingxiang Yong; Cao Xi; Mian Tao; Jeffery Lo; Ricky Lee
-
Cover Image
Cover Image

Verification of Compartmental Electromagnetic Interference Shielding Effect with imprint-Through Mold Via (i-TMV) for RF modules
Motohiro Negishi, Tomoaki Shibata, Xinrong Li, Naoya Suzuki
Emergence of Glass Solutions for 5G and Heterogeneous Integration
Aric B. Shorey, Shelby F. Nelson, David Levy, Paul Ballentine
Fine-pitch Copper Pillar Flip Chips in High Reliability Applications
Catherine Farnum, Kaysar Rahim, Ph.D.
Highly accelerated lifetime testing in power electronics
Bernhard Czerny, Golta Khatibi
Implementation of Trusted Manufacturing & AI-based process optimization into microelectronic manufacturing research environments
K.-F. Becker, S. Voges, P. Fruehauf, M. Heimann, S. Nerreter, R. Blank, M. Erdmann, S. Gottwald, A. Hofmeister, M. Hesse, M. Thies, S. Mehrafsun, R. Fust, E. Beck, J. Pawlikowski, B. Schröder, C. Voight, T. Braun, M. Schneider-Ramelow