In this study, the heterogeneous integration of two chips on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the materials, design, process, fabrication, and reliability of the package. Drop test and results of the package are also provided.

For 2.1D IC integration, thin-film layers (the coreless substrate) with fine metal line width (L) and spacing (S) are fabricated directly on the top layer of a build-up package substrate and become a hybrid substrate [16]. In this case, the yield loss of the hybrid substrate, especially the fine metal L/S coreless substrate, is difficult to control and can be very large. The very first 2.3D IC integration structural patent (US 9,484,319, filed on December 23, 2011) was granted to Statschippad [7]. The structure consists of a build-up package substrate (or high-density interconnect), solder joints with underfill, and a fine metal L/S redistribution-layer (RDL)-substrate (or thin-film substrate/interposer) [721]. [712] are with chip-first fan-out packaging process while [1321] are with chip-last (or RDL-first) fan-out packaging process. For 2.3D IC integration with chip-last fan-out packaging process, the fine metal L/S RDL-substrate and the build-up package substrate are fabricated separately [1321. In [1318], they build the fine metal L/S RDL-substrate first, then bond the chips on the fine metal L/S RDL-substrate, and finally assemble the module (chips + fine metal L/S RDL-substrate) on the build-up package substrate. However, in [1921], the fine metal L/S RDL-substrate and the build-up package substrate are first interconnected into a hybrid substrate through the solder joints, which are enhanced with underfill. Then, they bond the chips on the known-good hybrid substrate. In this case, the yield loss of the hybrid substrate, especially the fine L/S coreless substrate, is easier to control and smaller.

In this study, the heterogeneous integration of one large chip (10 mm × 10 mm × 150 μm) and one smaller chip(5mm × 5mm × 150 μm) on a hybrid substrate is investigated. Emphasis is placed on the design, materials, process, fabrication, and drop test (1,500 G/ms) of the heterogeneous integration chip/package assembly. The hybrid substrate is basically a 2.3D IC integration that consists of (1) a fine metal L/S RDL-substrate (32 μm thick) with minimum metal L/S = 2 μm, (2) Sn3Ag0.5Cu solder joints and underfill interconnection layer, and (3) a 2-2-2 build-up package substrate (1.3 mm thick).

Fig. 1 shows the cross section of the test chips under consideration. The size of the large chip is 10 mm × 10 mm × 150 μm and there are 3,592 area array pads that are daisy chained. The small chip is 5 mm × 5mm × 150 μm and with 1,072 area array daisy chained pads. For both chips, the pitch of the outer peripheral pads is 50 μm and of all the inner pads is 200 μm.

The wafer bumping of the large and small chips is with the standard physical vapor deposition (PVD) for seed layer and electrochemical deposition (ECD) for Cu and solder process [22, 23]. Then, dice the wafers into individual bumped chips. It can be seen from Fig. 1 that the Cu pad size is 40 μm × 40 μm, the Ti/Cu (0.1/0.2 μm) UBM (under bump metallurgy) pad size is 32 μm diameter, and the passivation (PI2) opening is 20 μm diameter. The diameter of the Cu pillar is 32 μm and its height is 22 μm, and the height of the SnAg solder cap is 15 μmplusa3 μm Ni barrier.

Fig. 2a schematically shows the test package. It can be seen there are two chips of the heterogeneous integration, namely the large chip (Chip 1, 10 mm × 10 mm) and the small chip (Chip 2, 5 mm × 5 mm). The spacing (gap) between the large chip and small chips is 100 μm. The chips are bonded on top of the hybrid substrate, which consists of the fine metal L/S RDL-substrate (20 mm × 15 mm × 32 μm) and build-up substrate (23 mm × 23 mm × 1.3 mm) as shown in Fig. 3.

The RDL-substrate has three RDLs and each RDL consists of one dielectric layer (DL) and one metal layer (ML). The line width and spacing of ML1, ML2, and ML3 of RDL1, RDL2, and RDL3, respectively, are 2/2 μm, 5/5 μm, and 10/10 μm as shown in Fig. 4(a). The thickness of ML1, ML2, and ML3 are 3 μm, 5.5 μm, and 8 μm, respectively. The thickness of DL01 (DL between the Cu pad and ML1), DL12 (DL between ML1 and ML2), and DL23 (DL between ML2 and ML3) are 3 μm, 5 μm, and 4.5 μm, respectively. The pad diameter and thickness are 35 μm and 6 μm, respectively. The V01 (via connecting between the pad and ML1) is 30 μm, V12 (via connecting between ML1 and ML2) is 30 μm, and V23 (via connecting between ML2 and ML3) is 38 μm. The solder mask (resist) opening and thickness are 80 μm and 1.5 μm, respectively. The temporary panel for fabricating the RDL-substrate for the heterogeneous integration of the two-chip package is shown in Fig. 4b. It can be seen that the panel size is 515 mm × 510 mm and is made of glass. The panel is divided into four strips and each strip (257.5 mm × 255 mm) has 154 (20 mm × 15 mm) RDL-substrates. Thus, in one shot, it can make RDL-substrates for 1,232 chips in 616 heterogeneous integration packages.

The top view and bottom view of the 20 mm × 15 mm RDL-substrate of the heterogeneous integration of the two-chip test package are shown in Fig. 5. It can be seen that:

  • There are 3,592 + 1,072 = 4,664 (36 μm) pads on the top of the RDL-substrate, Fig. 5a. These pads are for the chips-to-substrate bonding.

  • There are 4,039 solder ball pads (105 μm diameter) on a 0.225 mm pitch at the bottom of the RDL-substrate, Fig. 5(c). The pads are solder mask defined (SMD) and the solder mask opening is 80 μm. These pads are for Sn3Ag0.5Cu lead-free C4 solder bump mounting and the solder ball diameter is 80 μm.

The process in fabricating the fine L/S RDL-substrate has been reported in [21]. Fig. 6 shows the SEM images of the RDLs including all three ML1, ML2, and ML3, where the designed and measured results are compared. It can be seen that there are some differences between the results and, in general, it is larger for the smaller metal L/S. Thus, there are rooms for improvements, e.g., a better estimation of the compensation of photoresist, laser direct imaging, ECD Cu, Cu etching, etc. For the via opening between MLs and between the ML and contact pad, the measured value (29 μm) is very close to the design N value (30 μm).

The build-up package substrate (23 mm × 23 mm × 1.3 mm) is a 2-2-2 structure as schematically shown in Fig. 7a. There are 4,039 pads on a 0.225 mm pitch on each substrate. It is fabricated on a 510 mm × 510 mm panel, Fig. 7b, by a conventional method. Fig. 7c shows a typical cross section image of the 2-2-2 build-up substrate. Figs. 7d and 7e show, respectively, the top view and the bottom view of the fabricated build-up package substrate panel.

Fig. 8 shows the individual build-up package substrate. Figs. 8a and 8b show, respectively, the schematic and fabricated top side of the package, whereas Figs. 8c and 8d show, respectively, the schematic and fabricated bottom side of the package. It can be seen that the top side of the package substrate matches with the bottom side of the RDL-substrate, Figs. 5c and 5d. There are 475 pads with 1 mm pitch on the bottom side of the substrate. The pad size is 500 μm and is SMD with the solder mask opening = 300 μm.

The C4 bumps are fabricated by stencil printing a Sn3Ag0.5Cu solder paste with a 29-μm-thick stainless steel stencil on top of the build-up package substrate. During solder reflow process, because of the surface tension of the molten solder, which creates smooth truncated spherical 30-μm-diameter solder bumps as shown in Fig. 9.

The warpage of the build-up package substrate (BU), fine metal L/S RDL-substrate with glass carrier RDL(G), and fine metal L/S RDL-substrate with organic carrier RDL(O) at various temperatures has been measured by the shadow Moire method via the Moire Platform. The results are shown in Fig. 10. It can be seen that the warpage of BU and RDL(G) is very small. However, the warpage of RDL(O) is very large compared with the others. (This is due to the thermal expansion mismatch between the glass carrier and the RDL-substrate is smaller than that between the organic carrier and the RDL-substrate.) Thus, in this study, the hybrid substrate will be formed by the combination of the build-up package substrate and the fine metal L/S RDL-substrate with the temporary glass carrier.

First, identify the location of the bumps on the package substrate and the pads on the RDL-substrate with glass carrier by using a lookup and lookdown camera; second, apply flux on both the bumps and pads; and third, pick and place the RDL-substrate with glass carrier on the package substrate then reflow. The top view of an assembled hybrid substrate is shown in Fig. 11. A typical SEM image of the hybrid substrate is shown in Fig. 12. It can be seen that the fine metal L/S RDL-substrate, solder joints, under-fill, and the build-up package substrate are properly assembled.

Before the final package assembly, we have to debond the glass panel to expose the bonding pads on the fine metal L/S RDL-substrate. By scanning a laser with 355 nm of wavelength on the glass, the sacrificial layer will become a powder and the glass carrier is removed. Then, chemical clean the surface.

Now that we have the microbumped chips (Fig. 1) and the hybrid substrate (Figs. 11 and 12) ready, it is time to do the final assembly. First, identify the location of the microbumps on the chips and the bonding pads on the hybrid-substrate by using a lookup and lookdown camera; second, apply flux on both the bumps and pads; and third, pick and place the chips on the hybrid substrate, then reflow. The assembled two-chip package is shown in Fig. 2b without underfill.

Underfill is applied to the flip chips on the hybrid substrate. The curing temperature, time, Young’s modulus, and CTE of the underfill are 160°C, 2 h, 12 GPa, and 22 × 10−6/°C (<Tg = 115°C), respectively. Figs. 13 and 14 (optical microscopy image and scanning electron microscopy image) show cross sections of the heterogeneous integration of two-chip package, which can be seen that the chip, microbumps, under-fill, RDL-substrate, C4-bumps, and build-up package substrate are reasonably done, even the chip bonding (leads to small amount of solder) has room to improvement. However, it is not the major focus of this study.

The drop spectrum is a half-sine pulse with the following conditions (Fig. 15): acceleration peak = 1,500 g, pulse duration N = 0.5 ms, velocity change = 468 cm/s, and drop height = 112 cm. The sample size is 33 packages. After 30 drops, there are 14 fails (19 pass). The failure criterion is when the measured resistance during the drop test reaches 1,000 ohms as shown in Fig. 16a. Less than that, it is considered no failure, as shown in Fig. 16b. After the continuity check and failure analysis, it is found that the failure locations and modes (cracks) are in the chips and solder joints (as shown in Fig. 17) [24] but not in the hybrid substrate (because the continuity check of the hybrid substrate itself is OK). These failures could be due to: (1) the large size of the package (20 mm × 15 mm), [25] (2) the size of the chips (10 mm × 10 mm and 5 mm × 5 mm), (3) the small thickness of the chip (150 μm), (4) the poor flip chip bonding of the microbumps (there is a very small amount of solder underneath the chips), and (5) the underfill (12 GPa) is too stiff (according to Table VI.2 of [26] the average Young’s modulus should be below 5 GPa). The present hybrid substrate is considered pass the drop test.

Some important results and recommendations are summarized as follows:

  1. The feasibility of heterogeneous integration of one large chip (10 mm × 10 mm × 150 μm) and one small chip (5 mm × 5mm × 150 μm) on a hybrid substrate has been demonstrated.

  2. The hybrid substrate consists of a fine metal L/S (2 μm/ 2 μm) substrate, an ordinary build-up substrate, and solder joints enhanced by underfill.

  3. The fine metal L/S substrate has been fabricated with the fan-out panel-level (RDL-first) process.

  4. The assembly of the hybrid substrate has been by stencil printing the SAC solder paste on the ordinary build-up substrate (in a panel format) and then by picking and placing the fine metal L/S substrates (with glass carrier) on the panel and reflowing.

  5. Chip-to-hybrid substrate final assembly has been performed by thermocompression bonding.

  6. The hybrid substrate has been shown to pass the drop test.

[1]
Shimizu
N.,
Kaneda
W.,
Arisaka
H.,
Koizumi
N.,
Sunohara
S.,
Rokugawa
A.,
and
Koyama
T.,
“Development of organic multi chip package for high performance application,”
IMAPS Proceedings of International Symposium on Microelectronics
,
2013
.
[2]
Oi
K.,
Otake
S.,
Shimizu
N.,
Watanabe
S.,
Kunimoto
Y.,
Kurihara
T.,
Koyama
T.,
Tanaka
M.,
Aryasomayajula
L.,
and
Kutlu
Z.,
“Development of new 2.5D package with novel integrated organic interposer substrate with ultra-fine wiring and high density bumps,”
IEEE/ECTC Proceedings
,
2014
.
[3]
Uematsu
Y.,
Ushifusa
N.,
and
Onozeki
H.,
Electrical transmission properties of HBM interface on 2.1-D system in package using organic interposer,”
IEEE/ECTC Proceedings
,
2017
.
[4]
Chen
W.,
Lee
C.,
Chung
M.,
Wang
C.,
Huang
S.,
Liao
Y.,
Kuo
H.,
Wang
C.,
and
Tarng
D.,
“Development of novel fine line 2.1 D package with organic interposer using advanced substrate-based process,”
IEEE/ECTC Proceedings
, pp.
601
606
,
May 2018
.
[5]
Huang
C.,
Xu
Y.,
Lu
Y.,
Yu
K.,
Tsai
W.,
Lin
C.,
and
Chung
C.,
“Analysis of warpage and stress behavior in a fine pitch multi-chip interconnection with ultrafine-line organic substrate (2.1D),”
IEEE/ECTC Proceedings
,
2018
.
[6]
Islam
N.,
Yoon
S.,
Tan
K.,
and
Chen
T.,
“High density ultra-thin organic substrate for advanced flip chip packages,”
IEEE/ECTC Proceedings
,
2019
.
[7]
Pendse,
R.,
“Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate,”
US 9,484,319 B2,
2016
.
[8]
Yoon
S.,
Tang
P.,
Emigh
R.,
Lin
Y.,
Marimuthu
P.,
and
Pendse
R.,
“Fanout flipchip eWLB (embedded wafer level ball grid array) technology as 2.5D packaging solutions,”
IEEE/ECTC Proceedings
,
2013
.
[9]
Chen,
N.,
“Flip-chip package with fan-out WLCSP,”
US 7,838,975 B2,
2010
.
[10]
Chen
N.C.,
Hsieh
T.,
Jinn
J.,
Chang
P.,
Huang
F.,
Xiao
J.,
Chou
A.,
and
Lin
B.,
“A Novel System in Package with Fan-out WLP for high speed SERDES application,”
IEEE/ECTC Proceedings
,
2016
.
[11]
Lin
Y.,
Lai
W.,
Kao
C.,
Lou
J.,
Yang
P.,
Wang
C.,
and
Hseih
C.,
“Wafer warpage experiments and simulation for fan-out chip on substrate,”
IEEE/ECTC Proceedings
,
2016
.
[12]
Yu,
D.,
“Advanced system integration technology trends,”
SiP Global Summit
,
SEMICON Taiwan
,
2018
.
[13]
Suk
K.,
Lee
S.,
Kim
J.,
Lee
S.,
Kim
H.,
Lee
S.,
Kim
P.,
Kim
D.,
Oh
D.,
and
Byun
J.,
“Low cost Si-less RDL interposer package for high performance computing applications,”
IEEE/ECTC Proceedings
,
2018
.
[14]
You
S.,
Jeon
S.,
Oh
D.,
Kim
K.,
Kim
J.,
Cha
S.,
and
Kim
G.,
“Advanced fan-out package SI/PI/thermal performance analysis of novel RDL packages,”
IEEE/ECTC Proceedings
,
2018
.
[15]
Chang
K.,
Huang
C.,
Kuo
H.,
Jhong
M.,
Hsieh
T.,
Hung
M.,
and
Wang
C.,
“Ultra high density IO fan-out design optimization with signal integrity and power integrity,”
IEEE/ECTC Proceedings
,
2019
.
[16]
Lai
W.,
Yang
P.,
Hu
I.,
Liao
T.,
Chen
K.,
Tarng
D.,
and
Hung
C.,
“A comparative study of 2.5D and fan-out chip on substrate: chip first and chip last,”
IEEE/ECTC Proceedings
,
2020
.
[17]
Fang
J.,
Huang
M.,
Tu
H.,
Lu
W.,
and
Yang
P.,
“A production-worthy fan-out solution – ASE FOCoS chip last,”
IEEE/ECTC Proceedings
,
2020
.
[18]
Lin
Y.,
Yew
M.,
Liu
M.,
Chen
S.,
Lai
T.,
Kavle
P.,
Lin
C.,
Fang
T.,
Chen
C.,
Yu
C.,
Lee
K.,
Hsu
C.,
Lin
P.,
Hsu
F.,
and
Jeng
S.,
“Multilayer RDL interposer for heterogeneous device and module integration,”
IEEE/ECTC Proceedings
,
2019
.
[19]
Miki
S.,
Taneda
H.,
Kobayashi
N.,
Oi
K.,
Nagai
K.,
and
Koyama
T.,
“Development of 2.3D high density organic package using low temperature bonding process with Sn-Bi solder,”
IEEE/ECTC Proceedings
,
2019
.
[20]
Murayama
K.,
Miki
S.,
Sugahara
H.,
and
Oi
K.,
“Electro-migration evaluation between organic interposer and build-up substrate on 2.3D organic package,”
IEEE/ECTC Proceedings
,
2020
.
[21]
Lau
J.H.,
Chen
G.,
Huang
J.,
Chou
R.,
Yang
C.,
Liu
N.,
and
Tseng
T.,
“Hybrid substrate byfan-outRDL-first panel-level packaging,”
IEEETransactionson CPMT
,
Vol. 11
,
No. 8
, pp.
1301
1309
,
2021
.
[22]
Lau
J.H.,
Fan-Out Wafer-Level Packaging
,
Springer
,
New York
,
2018
.
[23]
Lau
J.H.,
Heterogeneous Integration
,
Springer
,
New York
,
2019
.
[24]
Lau
J.H.
and
Lee
N.C.,
Assembly and Reliability of Lead-Free Solder Joints
,
Springer
,
New York
,
2020
.
[25]
Lau
J.H.,
Semiconductor Advanced Packaging
,
Springer
,
New York
,
2021
.
[26]
Lau
J.H.,
Low-Cost Flip Chip Technologies
,
McGraw-Hill
,
New York
,
2000
.