Sixty Earth-Day Test of a Prototype Pt/HTCC Alumina Package in a Simulated Venus Environment

The development of durable semiconductor integrated circuits (ICs) and associated packaging and integration technologies for long-term exploration of the surface of Venus is challenging because of the high temperature (460°C), high pressure (9.4 MPa), and chemically corrosive atmosphere of the planet [1–5]. After experimental investigation of high-temperature dielectric properties of a selected high-temperature cofired ceramic (HTCC) alumina in a temperature range from room temperature to 550°C, a packaging material system composed of this HTCC alumina with cofired platinum (Pt) metallization was proposed for use with high-temperature harsh environment devices [6]. A prototype ceramic package with 32-I/O (input/output) and a compatible circuit board based on this HTCC material system have been developed and successfully tested [7] with multiple analog and digital silicon carbide (SiC) high-temperature semiconductor ICs (developed at NASA Glenn Research Center) in 500°C Earth air ambient for more than 10,000 hours [8, 9], and short-term–tested at temperatures above 800°C [10]. To examine the possibility of using this packaging material system for long-term exploration of Venus surface with temperature of 465°C, and a corrosive atmosphere at ~90 bar pressure, an HTCC alumina packaging substrate with cofired surface Pt metallization was previously tested with a SiC IC in simulated Venus atmospheric conditions for three Earth weeks [11, 12].

This article discusses further and more in-depth testing of a customized prototype HTCC alumina package with Au/Pt metallization with prolonged exposure to a simulated Venus environment. Before the 60-d simulated Venus environment exposure (Phase 3), the package (and packaged SiC IC) was first subjected to 48 h in 460°C Earth air (Phase 1) followed by 48 h in 460°C at 90 bar N₂ (Phase 2). The testing in the simulated Venus environment and high-temperature pressurized nitrogen was implemented in the NASA Glenn Extreme Environment Rig (GEER) [13]. The results of measured electrical insulation resistance between a pair of I/Os of the prototype package in the three-phase test and posttest diagnostic analysis are presented and discussed in this article. Initial analytical results of material surfaces of the package after exposure to the Venus environment are presented and discussed to evaluate the stability of the packaging material system in the Venus environment and the surface conditions after the test. It has been briefly reported earlier that both packaged SiC ICs were tested successfully and operated throughout the entire test duration, including 60 d in Venus surface atmospheric conditions [14], and the observed electrical behavior of both circuits has been reported more recently in detail elsewhere [15].

The ceramic electronic package (and the packaged SiC IC) was electrically connected to the measuring instruments outside of the GEER chamber via a custom-constructed high-temperature high-pressure feedthrough with a stainless steel tube of outer diameter of ¾ in. [16]. To be integrated into this stainless steel tube with the inner diameter.65 in. (of this feedthrough), a 32-I/O HTCC alumina package, measured as 1.075 in. × 1.075 in. × .1 in. [7], with Pt metallization, was diced using a diamond saw into three parts. The center part resulting from dicing the HTCC package was removed, and the two end parts, with eight usable bond pads each, were joined using a high-temperature thick-film glass material to form a smaller package (Fig. 1). Eight original pads with 50-mil pitches on each longer side of the package were connected by wires on the backside, forming four pairs of independent pads (two neighboring pads were shorted to each other by attaching a 10-mil Au wire to both pads) (four pads on two shorter sides, as shown in Fig. 1, were not usable). Two such test packages were made for this test. One of the two packages (designated as “Package 5”) was electrolysis-coated with a thin Au layer with 100 microinches thickness on exposed Pt metallization (about 5 microns) surfaces before dicing. The second package (designated “Package 4”) was coated with thick-film Au on the surfaces of Pt metallization pads used for the test. The packages were reinforced, using the thick-film glass material as adhesive, with a small ceramic alumina dice mounted on the backside of the package along the seam line for better mechanical integrity. After the glass was cured at 850°C, an alumina-based adhesive [17] was applied between the ceramic dice over the seam line on the backside and cured at a final temperature stage at 371°C for 2 h. The completed package measured 1.075 in. × .5 in. × .1 in. (small dice not included). Eight gold (Au) wires with a diameter of 10 mil were then attached to Au/Pt metallization pads on the backside of the package using gold paste fired at 850°C in air ambient; four wires were on each long side of the package as shown in Fig. 1. Each Au wire was connected/attached to two neighboring backside pads. A SiC ÷2/÷4 clock IC with a half/quarter frequency selection die [9] was attached to each package using Au paste [18, 19] cured at 600°C for 2 h. One-mil-diameter Au wire bonds (a few of which are barely visible in Fig. 1) connected the SiC IC to the package bond pads. Ball-wedge wire bonds were used to connect the SiC die to the package; ball bonds were applied on SiC die pads, and wedge bonds were applied on package pads. The eight 10-mil Au wires were individually spark-welded to eight 20-mil-diameter Au wires extending from the inside-GEER end of the stainless tube, as shown in Fig. 2, to the feedthrough (not shown). Each 20-mil Au was individually insulated using fiber glass sleeves. Six of these wires connected the SiC IC to the measuring instruments. Two wires (designated as “Wire 4” and “Wire 5,” attached to two separated package pads) were not connected to the SiC IC or each other, but were connected to two separate 20-mil-diameter Au wires running through the stainless steel tube and the feedthrough for the purpose of monitoring the electrical insulation resistance of the feedthrough in parallel with the package throughout the course of the three-phase harsh environment testing. The packages (packaged SiC ICs) were “facing down” in the stainless steel tube, as shown in Fig. 2. The test was conducted without a lid on the ceramic package, so packaging components, including the die attach, wire bonds, and metallization patterns, and SiC ICs were fully exposed to the testing environments.

In addition to the electrical testing of the packaged SiC ICs, DC insulation resistances between Wires 4 and 5 of both test assemblies were measured to evaluate the parasitic leakage of the package and wiring system in all three phases of the environmental testing. The I-V curves between Wires 4 and 5 of both assemblies were measured via the other ends (outside-GEER) of 20-mil Au wires of the feedthrough using a computer-controlled Keithley 2400 source-measurement unit (SMU); data were acquired with the integration time of the SMU set at 16.67 ms, and the time delay between two voltage steps was set at .1 s. The electrical resistance was calculated from the slope of the I-V curve below the compliance current limit setting of the SMU. Most I-V curves were scanned between 0 and 50 V, but in some cases, the scanning voltage range had to be reduced to keep measured currents below the SMU compliance current limits. The slope of the best linear fit of the I-V curve (before the current reached the 1-mA compliance current limit set to the SMU) was used to extract the total resistance between Wires 4 and 5. Because the insulation resistance between Wires 4 and 5 of the package was measured at the other ends of the feed-through wires, the measured resistance data include the resistance between Wires 4 and 5 of the package in parallel with the insulation resistance between the two 20-mil-diameter Au wires running through the stainless steel tube and the feed-through. Ideally, the electrical insulation resistance measured between Wires 4 and 5 throughout testing should be an open circuit well above 1 GΩ (with low leakage or cross talk of electrical signal between these two wires). The insulation resistance was first characterized throughout Earth air ambient from room temperature to 465°C (Phase 1) before loading the test assemblies onto the GEER, followed by Phase 2 in high-pressure N₂ (GEER N₂), and Phase 3 in the simulated Venus surface environment in GEER. The measurements of insulation resistance were also performed during upward and downward temperature ramps.

The GEER chamber is a 3-ft-diameter and 4-ft-long cylindrical stainless steel pressure vessel designed for long-duration testing parts in extreme conditions. The simulated Venus atmospheric environment is achieved with a fully automated high-pressure gas delivery system, multicomponent gas mixer, and high-pressure gas pump. The chamber is uniformly heated by internal electric heaters that are controlled by the facility programmable logic controller. This test in GEER included two test phases (Phases 2 and 3), a brief test cycle (Phase 2) with nitrogen, followed by a 60-d test with the simulated Venus gas mixture (Phase 3) [11, 12]. The GEER chamber was first purged with dry nitrogen gas and evacuated to .1 bar to reduce gas impurities. The vessel was then filled to 36.5 bar at ambient temperature with pure nitrogen and heated at 7°C/h to the target conditions of 460°C temperature and 92 bar pressure (the pressure increased with temperature). The conditions were held for 48 h before transitioning to Phase 3 with the simulated Venus environment. Before filling with the simulated Venus gas mixture, the vessel temperature was reduced to 150°C and then depressurized to 1 bar. Next, the Venus simulating gas mix was automatically filled in the quantities needed to achieve the mixing ratios listed in Table I. The vessel temperature was held at 150°C during the filling process. Once all constituents were delivered to the vessel, the simulated Venus gas mixture was heated at 7°C/h until reaching the target test conditions of 92 bar at 460 ± 5°C. The test in the simulated Venus environment lasted 60 Earth days during which the gas mixture was periodically sampled and adjusted to the targeted mix ratios. The gas mix of the simulated Venus environment is shown in Table I [11, 12].

After the test in GEER, ceramic Package 5 was examined by x-ray photoelectron spectroscopy (XPS), focused ion beam (FIB) cross-section milling, and field-emission scanning electron microscopy (FE-SEM)/energy-dispersive x-ray spectroscopy (EDS) to study the durability of the package materials and surface conditions after long-term exposure to the simulated Venus surface environment. XPS analysis was performed on a PHI 5000 VersaProbe using monochromatic microfocused Al x-rays (43.4 W) and a hemispherical electron energy analyzer with a photoelectron takeoff angle of 45° and 200-μm-diameter area of analysis. The FE-SEM imaging and FIB cross-section milling were carried out in an FEI Helios NanoLab™ 650 Ga dual-beam FIB equipped with an Oxford Instruments 80mm² XEDS silicon drift detector system. A thin Pt layer was deposited on the analysis area to protect the cross section during milling. A focused Ga beam of 30 keV was used for milling, and a 2–5 keV e⁻ beam was used for FE-SEM and EDS data acquisition.

It is an intended open circuit between Wires 4 and 5, so ideally the resistance between Wires 4 and 5 should be very high and independent of temperature and time. However, the insulation resistances of both assemblies measured during all three phases of testing changed substantially with temperature and testing time.

Fig. 3 shows the measured insulation resistances between Wires 4 and 5 of Assemblies 4 and 5 as functions of temperature in Earth air ambient, GEER nitrogen, and GEER Venus conditions. The data chart presents the temperature-dependent resistances of both assemblies during the upward temperature ramp toward 460 ± 5°C, constant temperature dwell at 460 ± 5°C, and downward ramp toward room temperature of all three phases of Earth Oven, GEER N₂, and GEER Venus conditions. The resistances of both assemblies decrease significantly with temperature increase for all the temperature ramps. The temperature dependence of resistances are approximately reversible in Earth air, but the changes in resistances in GEER N₂ and GEER Venus conditions are largely not reversible. It is noteworthy that in the Earth air phase, the pressure is constantly 1 atm, but the pressure in GEER N₂ increases with temperature and reaches 90 bar when the temperature reaches 460 ± 5°C. The insulation resistances of both assemblies decrease severely in Phase 3 GEER Venus conditions and are not reversible. The total drops of insulation resistances, after the three-phase test, are more than five orders of magnitude.

The insulation resistances also decrease at 460 ± 5°C with testing time. Fig. 4 shows the measured insulation resistances between Wires 4 and 5 of Assemblies 4 (blue) and 5 (green) versus time with the packages (and connecting wires) at 460 ± 5°C ambient temperature during all three testing phases. As shown in Fig. 4, for the first testing phase in 460 ± 5°C Earth air, the insulation resistance of Assembly 5 with Package 5 is initially 7.9 MΩ and increases to 650 MΩ after 48 h at this temperature, whereas the Assembly 4 insulation resistance is initially at 210 MΩ and increases to 3.0 GΩ.

In the second phase test in GEER N₂ at 90 bar, the insulation resistances vary with time at 460 ± 5°C negatively, exhibiting substantial degradation. In particular, the resistance of Assembly 5 starts at 384 MΩ and sharply decreases almost three orders of magnitude to 448 kΩ at 48 h in GEER N₂ at 90 bar as shown in Fig. 4, whereas the insulation resistance of Assembly 4 similarly decreases from 424 to 7.6 MΩ. Because N₂ is generally regarded as a mostly inert gas, the large degree of insulation resistance degradation over the time at 460 ± 5°C was unanticipated.

In Phase 3, GEER Venus conditions, the measured assembly insulation resistances continue the downward trend. As shown in Fig. 4, the resistance of Assembly 5 is 45 kΩ in the 460 ± 5°C GEER Venus condition initially and further decreases to 721 Ω as the minimum measured resistance at 231 h, before gradually increasing to 2.26 kΩ at 1,459 h (60 d) in the GEER Venus condition, whereas the resistance of Assembly 4 declines from 1.18 MΩ to 19.8 kΩ in GEER Venus conditions.

After the final GEER test phase, Assembly 5 was removed from GEER for posttest disassembly and investigation to uncover the mechanisms of the measured severe degradation of “open-circuit” insulation resistance. Toward this end, a series of SMU I-V curves of Assembly 5 were measured as Assembly 5 was systematically taken apart. Before the disassembly, the room-temperature insulation resistance between Wires 4 and 5 of Assembly 5 terminals was measured to be 12 kΩ.

The critical configuration for postGEER-test diagnostic I-V measurement is depicted in Fig. 5; the resistance between Wires 4 and 5 of ceramic Package 5 was measured following its disconnection (i.e., physical and electrical isolation) from the rest of Assembly 5. The ceramic package resistance between Wires 4 and 5 measured at room temperature by directly clipping the 10-mil-diameter Au wires as depicted in Fig. 5 was 21.7 MΩ. Meanwhile, the resistance measured between the corresponding long fiberglass-insulated 20-mil-diameter Au wires running through the stainless steel tube and pressure seals (now entirely disconnected from the ceramic Package 5 leads) was only 12 kΩ, indicating that the (20-mil Au) wire insulations permanently degraded substantially during the test. The work on wiring insulation and feedthrough technology for the Venusian environment will be reported separately elsewhere.

Although the results of the abovementioned measurements clearly exclude the HTCC ceramic package as the primary source of observed “open-circuit” insulation resistance degradation, the insulation resistance between Wires 4 and 5 of post-GEER-test Package 5 at room temperature is nevertheless substantially and permanently degraded to 21.7 MΩ. Therefore, material analysis described in the following section was conducted to see if physical evidences responsible for degraded insulation resistance could be observed.

Fig. 6 shows the EDS elemental map of a package bond pad and the surrounding HTCC alumina surface. The yellow, green, and blue colors indicate distributions of Pt, S, and Al, respectively. In the area of Box 16 of the bond pad, as labeled in Fig. 6, the weight percentage of Pt, Au, S, and Al measured by EDS (C, O, and Al are also in the EDS spectrum and counted in percentage) is 47.1%, 36.4%, 9.4%, and 1.1%, respectively. EDS of a cross section of the bond pad generated by FIB (not shown) indicates that a thin nonuniform surface layer of PtS resulted from the reaction between the Pt bond pad and the sulfur-containing gas(es) in the simulated Venus environment, but the underlying Pt is not reacted. In Box 23 of the alumina surface close to the Pt pad, the weight percentage of Pt, S, C, and Al (O, Si, and Mg are also shown in the EDS spectrum and counted in percentage) is 1.2%, .5%, 1.9%, and 53.4%, respectively. Fig. 7 shows the FE-SEM micrograph of the alumina surface of −45 μm × 25 μm on the left side of the bond pad shown in Fig. 6. Scattered particles of PtS and alkaline earth impurities from the alumina are shown in Fig. 7. The EDS elemental map (not shown) of Pt, Au, and S of the Pt bond pad shows that the distribution of Au, originally uniformly coated on the top surfaces of the Pt pads, is no longer uniform and continuous.

XPS of the exposed cofired alumina surface of Package 5 shows the presence of C, S, F, Na, Mg, Ca, Si, Fe, and trace amounts of Pt, in addition to O and Al. The relative atomic surface concentrations of these elements before surface sputtering are shown in Table II. After a 1-min Ar⁺ surface sputtering, the surface carbon is significantly reduced and Ca is eliminated. The relative atomic concentrations of remaining elements are shown in Table II.

The FE-SEM and EDS results of the Pt pads show that even though a thin surface layer of PtS formed on the bond pads, underlying Pt remained chemically stable in the metal state. Because of the reaction on the top surface of the bond pad, the Au coating layer largely diffused and redistributed non-uniformly. The surface color of the bond pads also changed from golden to gray as shown in Figs. 1 and 5. If these surface reaction and surface phenomena are strictly contained on bond pad surfaces, they may not have a direct and significant impact on the electrical performance and packaging reliability. The mechanism of formation of the PtS/Pt particles on the alumina surface near bond pads still needs to be investigated. It is unlikely that the insulation resistance between neighboring pads of the package is significantly reduced by these scattered and isolated PtS/Pt particles alone.

The results of the XPS study of the HTCC alumina surface indicate that although the alumina was stable in the simulated Venus environment, its surface was contaminated by carbon and possibly multiple ionic compounds that may elevate surface electrical conductivity, which may account for the observed degradation of insulation resistance.

Two customer test packages based on a previously developed HTCC alumina package with Pt metallization have been tested for the first time in a simulated Venus environment for 60 Earth days. The bulk material system composed of high-temperature cofired Pt and 92% alumina has been shown to be chemically stable in a long-term simulated Venus environment. The formation of a thin and discontinuous top surface layer of PtS was observed on originally Au-coated Pt bond pads. Both packages successfully facilitated the test of SiC ICs in the simulated Venus environment, but the package electrical insulation resistance substantially degraded, possibly caused by surface contaminations resulting from reactions of the impurities in alumina with Venus gases at high temperature and high pressure, as well as possible surface depositions from the simulated Venus environment. Surface encapsulation with low parasitic effects to protect Pt metallization and alumina surfaces is suggested to be investigated to further improve the electrical performance and longer term reliability of the Pt/HTCC alumina packaging system for possible Venus surface applications.

The authors thank Amir Avishai at Case Western Reserve University for FIB and SEM/EDS analysis; Michelle M. Mrdenovich for technical assistance; and Carol M. Tolbert for her suggestion. The authors are grateful to Diana Centeno-Gómez, Félix A. Miranda, and Dawn C. Emerson for their contributions and proofreading the manuscript. This work was funded by the NASA Long-Lived In-situ Solar System Explorer (LLISSE) project, sponsored by the NASA Science Mission Directorate. This article was originally presented in the 2018 iMAPS International Conference and Exhibition on High Temperature Electronics (HiTEC 2018), Albuquerque, NM, May 8–10, 2018.